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rev. 2.1 nov. 1996 users manual hyundai microelectronics GMS84512 / 84524 8-bit single chip microcomputer
GMS84512/84524 user ? s manual table of contents 1. overview 2. cpu 3. peripheral function 4. control function 5. support tool 6. appendix
1. overview 1. features 2. block diagram 3. summary of peripheral function register 4. pin assignment 5. pin description 6. terminal types 2. cpu 1. registers 2. memory space 3. peripheral function 1. port 2. clock generation circuit 3. timer 4. a/d comparator 5. serial i/o 6. pwm 7. interrupt interval measurement circuit 8. on screen display 4. control function 1. interrupts 2. standby function 3. reset function 5. support tool 1. emulator 2. debugger 3. assembler 4. linker 5. font editor 6. otp chip 6. appendix l electrical data l package outline
gms 84512 / 84524 1 - 1 an 8-bit microcomputer using the g8mc core is a single-chip microcomputer including several peripheral functions such as timer, i/o comparator, serial i/o, pwm, watch-dog timer and on-screen display. 1.1 features l rom 12,288 bytes ( GMS84512 ) 24,576bytes ( gms84524 ) l ram 256 bytes l minimum instruction execution tim e 1 us ( @ xin = 4 mhz ) l i/o port 42 ( input: 3, output: 10, i/o: 29 ) l serial i/o 8-b it x 1 ch. ( 1mhz, 500khz, 250 khz, ext. clock ) l a/d comparator 5-bit x 4 ch. ( max. 1 lsb ) l pulse width modulation 14-bit x 1 ch. 7-bit x 8 ch. l timer - timer/counte r 8 bit x 4 ch. ( 16-bit x 2 ch is acceptable) - basic interval time r 8 bit x 1 ch. - watch dog timer l interrupt interval estimation circuit for remocon signal receiving l interrupt sources 14 sources l pulse ( t2048 ) output function period : 2,048 us, duty: 50 % l on screen display - kinds of character 128 kinds (in clude 2 test characters) - construction of character 14 dots x 18 dots - size of character 4 x 4 kinds - number of display character 22 characters x 3 lines ( max. 12 lines) - display colors 8 kinds - color edge, smoothing function l power save mode stop m ode l operating voltage 4.5 ~ 5.5 v l package 52 sdip l otp chip GMS84512t/84524t
gms 84512 / 84524 1 - 2 1.2 block diagram r40 ~ r45 g8mc core r20 ~ r27 r2 port r32 ~ r37 r3 port r00 ~ r07 r0 port r10 ~ r16 r1 port r50 ~ r53 r5 port pwm a/d comp. r53/ y r52/ b r50/ r r51/ g r15/ cin1 r16/ cin2 r43/ pwm2 r42/ pwm3 r45/ pwm0 r44/ pwm1 r37/ pwm6 r36/ pwm7 r41/ pwm4 r40/ pwm5 r32/ pwm8 r26/ ec2 r27/ ec3 r33/ sout r35/ sin/ cin3 r34/ sclk interrupt controller remocon timer serial i/o clock gen./ system con. osd r30/ int1 r31/ int2 hd vd r17/ cin0/ int3 osc2 osc1 vdd test xin reset vss xout ram ( 256 byte ) watch dog timer r30 ~ r31 r17 r4 port rom ( 12k / 24k) prescaler / b.i.t.
gms 84512 / 84524 1 - 3 1.2 peripheral function overview block function index prescaler / b.i.t. prescaler is consists of 10 bits binary counter, and divide oscillation clock. the divided output from each bit of prescaler provided to peripheral hardware. b.i.t a 8 bit binary counter has a function such as security of oscillation stabilization time, generation of basic interval time interrupt as watch function, providing the clock for watch-dog timer 3 - 13 watch-dog -timer wdt is consist of 6-bit binary counter, wdtr(watch-dog timer register), and comparator, input clock of wdt is provided by basic interval timer interrupt and maximum output cycle is 4 seconds. when wdtom is ? 1 ? , the output of wdt reset the device. 3 -16 timer / counter timer is an 8 bit binary counter and consisted of t0, t1, t2, t3. as an 8-bit binary counter, each t0, t1 can be used 16-bit interval timer to connect each other. as an 8 bit binary counter/event counter each t2, t3 can be used 16-bit/event counter to connect each other. at 4 mhz oscillation, maximum interval time of t0 is 8.192 ms, t1 is 2048 ms, t0-t1 is about 2 seconds, t2 is 2.048 ms, t3 is 51 2 u s ,t2-t3 is about 0.5 seconds 3 - 19 a/d comp- arator a/d comparator has 5 bit resolution, and 4 input channel. it has sample and hold function of input. at 4 mhz it takes about 8 u s to compare. error is less than 1/2 lsb. 3 - 26 serial i/o it is 8 bit clock synchronous serial interface unit, the clock transmission cycle is 1 us , 2 us , 4 us which can be selected external clock. when iosw(bit 6 of serial i/o mode register) is ? 1 ? , r33 pin operates sout at transmission mode, sin at receiving mode. 3 - 28 pwm ( pulse width modulation ) pwm is consists of 14 bit pwm 1 ch and 7 bit pwm 8 ch. 14 bit pwm has 0. 5 us minimum resolution width, 819 2 us cycle time, 7 bit pwm has 8 us minimum resolution 8 us , 102 4 us , cycle time. the polarity of pwm output can be assign by software. 3 - 32 interrupt interval measurem- ent circuit interrupt interval measurement circuit consists of 8 bit binary counter, interrupt interval saving circuit. it can select 3 2 us , 6 4 us as a measurement clock . because it can select external signal edge, measurement of input signal cycle or pulse width is possible. so it can be used remocon receiving. 3 - 38 osd ( on-screen- display ) maximum number of character or symbol displayed in crt is 128 basically displayed by 22 character sx 3 lines. maximum 12 lines is possible with osd interrupt. osd clock can use 4 mhz ~ 8 mhz size of display character is 16 kinds, it can be used by line unit. the color of display character is 8 kinds it can be used by character unit. in display mode, there are character mode, background mode, color mode, and blanking mode, it can be used by line unit especially smoothing function and osd oscillator control function exists. 3 - 41
gms 84512 / 84524 1 - 4 1.4 pin assignment 1 hd 52 r50/ r 2 vd 51 r51/ g 3 r45/ pwm0 50 r52/ b 4 r44/ pwm1 49 r53/ y 5 r43/ pwm2 48 r00 6 r42/ pwm3 47 r01 7 r41/ pwm4 46 r02 8 r40/ pwm5 45 r03 9 r37/ pwm6 44 r04 10 r36/ pwm7 43 r05 11 r35/ sin/ cin3 42 r06 12 r34/ sclk 41 r07 13 r33/ sout 40 r10 14 r32/ pwm8 39 r11 15 r31/ int2 38 r12 16 r30/ int1 37 r13 17 r27/ ec3 36 r14 18 r26/ ec2 35 r15/ cin1 19 r25/ t2048 34 r16/ cin2 20 r24 33 r17/ cin0/ int3 21 r23 32 r20 22 r22 31 r21 23 test 30 reset 24 xin 29 osc1 25 xout 28 osc2 26 vss 27 vdd hme GMS84512/84524
gms 84512 / 84524 1 - 5 1.5 pin description classification no. symbol i/o function type remark power 27 vdd input power supply (4.5~5.5v) 26 vss input ground (0v) system 23 test input test input pin control or at 'l' input: single chip mode ia clock at 'h' input : test mode 24 xin input crystal connection pin (with xout) if an external clock is used, xin pin should be connected external clock source 25 xout output crystal connection pin(with xin) if an external clock used, xout pin should be open 30 reset input in the state of 'l' level, system ia enter the reset state osd 1 hd input horizontal synchronizing signal input pin ia 2 vd input vertical synchronizing signal input pin 28 osc2 ouptut clock output for osd 29 osc1 input clock input for osd 49 y output switching signal output pin r53 share 50 b output blue signal output pin oa r52 share 51 g output green signal output pin r51 share 52 r output red signal output pin r50 share pwm 3 pwm0 output pulse width modulation output pin r45 share 4 pwm1 output (7bit pwm) r44 share 5 pwm2 output ob r43 share 6 pwm3 output r42 share 7 pwm4 output r41 share 8 pwm5 output r40 share 9 pwm6 output iof r37 share 10 pwm7 output r36 share 14 pwm8 output 14bit pwm output pin iod r32 share 19 t2048 output pulse(2048us) output pin r25 share sci 11 sin input serial data input pin ioe r35 share 12 sclk i/o serial clock i/o pin iog r34 share 13 sout output serial data output pin r33 share timer 17 ec3 input event counter input pin iob r27 share
gms 84512 / 84524 1 - 6 classification no. symbol i/o function type remarks interrupt 15 int2 input external interrupt request input pin ib r31 share 16 int1 input (int1,int2 : remocon input capture r30 share 33 int3 input input possible) ic r17 share a/d 11 cin3 input analog input pin ioe r35 share comparator 33 cin0 input (default selection : cin0) ic r17 share 34 cin2 input ioc r16 share 35 cin1 input r15 share i/o port 41 r07 i/o r0 port ~ ~ (can assigned i/o state bit by bit by r0dd) ioa 48 r00 i/o 33 r17 input r1 port ( r17 input only ) ic cin0/int3 share 34 r16 i/o ( 7 ports of r10~r16 can assigned i/o ioc cin2 shrae ~ ~ state bit by bit by r1dd cin1 share 40 r10 i/o ioa 17 r27 i/o r2 port iob ec3 share 18 r26 i/o ( can assigned i/o state bit by bit ec2 share 19 r25 i/o by r2dd) iod t2048 share 20 r24 i/o 21 r23 i/o 22 r22 i/o ioa 31 r21 i/o 32 r20 i/o 9 r37 i/o r3 port iob pwm6 share 10 r36 i/o ( 6 bits of r31~r32 can assigned i/o pwm7 share 11 r35 i/o state bit by bit by r3dd ioe sin/cin3 share 12 r34 i/o iog sclk share 13 r33 i/o sout share 14 r32 i/o iod pwm8 share 15 r31 input ( r30,r31 is input only) ib int2 share 16 r30 input int1 share 3 r45 output r4 port pwm0 share 4 r44 output ( 6 bit output only ) pwm1 share 5 r43 output ob pwm2 share 6 r42 output pwm3 share 7 r41 output pwm4 share 8 r40 output pwm5 share 49 r53 output r5 port y share 50 r52 output ( 4 bit output only ) oa b share 51 r51 output g share 52 r50 output r share
g ms 84512 / 84524 1 - 7 1.6 terminal types pin terminal type at reset xin xout oscillation osc1 osc2 oscillation stop reset hd vd test ( ? l ? ) hi-z r30/ int1 r31/ int2 hi-z r17/ cin0 / int3 hi-z ia type ib type int1,int2 data bus i vdd vss rd schmitt input ic type int1,int2 data bus i vdd vss rd schmitt input cin3 test pin is using normal gate schmitt input rst h sync v sync i vdd vss vss xin xout vdd vdd vss vdd vss osdon vss vss xin xout vdd vss vdd vss vdd vss stop vss
gms 84512 / 84524 1 - 8 pin terminal type at reset r50/ r r51/ g r52/ b r53/ y hi-z r45/ pwm0 r44/ pwm1 r43/ pwm2 r42/ pwm3 r41/ pwm4 r40/ pwm5 hi-z r0 0~ r07 r1 0~ r14 r2 0~ r24 hi-z r26/ ec2 r27/ ec3 hi-z oa type ob type ioa type iob type data reg. data bus pwm 0 ? - pwm5 vss selection mux o vss vdd vss vdd vss data bus r, g, b, y selection mux o data reg. data bus vss vdd vss data bus mux io direction reg. vdd data bus data reg. rd ec2, ec3 schmitt input data bus vss vdd vss data bus mux io direction reg. vdd data bus data reg. rd
g ms 84512 / 84524 1 - 9 pin terminal type at reset r15/ cin1 r16/ cin2 hi-z r25/ t2048 r32/ pwm8 hi-z r35/ sin / cin4 hi-z ioc type iod type ioe type cin1, cin2 data bus vss vdd vss data bus mux io direction reg. vdd data bus data reg. rd rd data bus vss vdd vss data bus mux mux io vdd selection t2048, pwm8 data bus data reg. direction reg. sin data bus vss vdd vss data bus mux io vdd selection data bus data reg. schmitt input direction reg. rd cin4
gms 84512 / 84524 1 - 10 pin terminal type at reset r36/ pwm7 r37/ pwm6 hi-z r34/ sclk r33/ sout hi-z data bus iof type iog type mux schmitt input rd rd data bus vss vss data bus mux io selection pwm6,pwm7 data bus data reg. direction reg. mux vss vss data bus io selection pwm6,pwm7 data bus data reg. direction reg. mux
GMS84512/84524 user ? s manual table of contents 1. overview 2. cpu 3. peripheral function 4. control function 5. support tool 6. appendix
gms 84512 / 84524 2 - 1 2.1. registers p rogram c ounter 15 8 pch 7 0 pcl a - register 7 0 a 15 8 y ( ya 16bit accumulator ) 7 0 a x - register 7 0 x y - register 7 0 y p rogram s tatus w ord 7 0 psw s tack p ointer *1 7 0 sp c arry flag z c h i g b n v z ero flag i nterrupt e nable flag h alf carry flag b reak flag g ( direct page ) flag o verflow flag n egative flag 15 8 *1 stack address ( 0100 h ~ - 013f h ) 01 h hardware fixed 7 0 sp
gms 84512 / 84524 2 - 2 2.1.1. a - register l 8 bit accumulator l in the case of 16-bit operation, compose the lower 8-bit of ya (16-bit accumulator) l in the case of multiplication instruction, execute as a multiplier register. after multiplication operation, the lower 8-bit of the result enters. (y * a ? ya) l in the case of division instruction, execute as the lower 8-bit of dividend. after division operation, quotient enters. (ya ? x ?? q: a , r: y ) 2.1.2. x- register l general-purpose 8-bit register l in the case of index addressing mode within direct page(ram area), execute as index register l in the case of g mode operation, execute as destination address register. the operation result enters into memory indirectly addressed by x register. l in the case of division instruction, execute as divisor register. 2.1.3. y- register l general-purpose 8-bit register l in the case of index addressing mode, execute as index register l in the case of 16-bit operation instruction, execute as the upper 8-bit of ya (16-bit accumulator). l in the case of multiplication instruction, execute as a multiplicand register. after multiplication operation, the upper 8-bit of the result enters. l in the case of division instruction, execute as the upper 8-bit of dividend. after division operation, quotient enters. l can be used as loop counter of conditional branch command. (e.g. dbne y, rel) 2.1.4. stack pointer l in the cases of subroutine call, interrupt and push, pop, reti, ret instruction, stack data on ram or in the case of returning, assign the storage location having stacked data. l stack area is constrained within 1-page (00h-ffh). page is fixed by h/w. user can only assign the lower address. at the initial stage, stack pointer should be initialized to
gms 84512 / 84524 2 - 3 point to ram area having h/w. ?interrupt reti subroutine call ret ? push a ( x, y, psw ) pop a ( x, y, psw ) m (sp) ?? ( pch ) sp ?? sp - 1 m (sp) ?? pcl ) sp ?? sp - 1 m (sp) ?? a m (sp) ?? ( pch ) sp ?? sp - 1 m (sp) ?? ( pcl ) sp ?? sp - 1 m (sp) ?? ( psw ) sp ?? sp - 1 sp ?? sp - 1 sp ?? sp + 1 ( pcl ) ?? m (sp) sp ?? sp + 1 ( pch) ?? m (sp) sp ?? sp + 1 a ? ? m (sp) ( psw ) ?? m (sp) sp ?? sp + 1 ( pcl ) ?? m (sp) sp ?? sp + 1 ( pch) ?? m (sp) sp ?? sp + 1
gms 84512 / 84524 2 - 4 2.1.5. program counter ( pc ) l program counter is a 16-bit counter consisted of 8-bit register pch and pcl. l addressing space is 64k bytes. l in reset state, reset routine address in address ffffh and fffeh enter into pc. 2.1.6. program status word( psw ) l psw is an 8-bit register. l consisted of the flags to show the post state of operation and the flags determining the cpu operation, initialized as 00h in reset state. psw ? carry flag ( c ) l after operation, set when there is a carry from bit7 of alu or there is not a borrow. l set by setc and clear by clrc. l executable as 1-bit accumulator. l branch condition flag of bcs, bcc. zero flag ( z ) l after operation also including 16-bit operation, set if the re sult is ? 0 ? . l branch condition flag of beq, bne. interrupt enable flag ( i ) l master enable flag of interrupt except for rst(reset). l set and cleared by ei, di . half carry flag ( h ) l after operation, set when there is a carry from bit3 of alu or there is not a borrow from bit4 of alu. l can not be set by any instruction. l cleared by clrv instruction like v flag. 7 n 6 v 5 g 4 b 3 h 2 i 1 z 0 c
gms 84512 / 84524 2 - 5 ? break flag ( b ) l set by brk (s/w interrupt) instruction to distinguish brk and tcall instruction having the same vector address. direct page flag ( g ) l assign direct page (0-page, 1-page). l set and cleared by setg, clrg instruction. l if used with pg2r( 00fc h ) it is enable to access 2-page ( osd ram ). g-flag pg2r direct page 0 - 0 - page access 1 0 1 - page access 1 2 - page access *notice : always after clearing, pg2r is enable to be accessed for it is the register of 0-page overflow flag ( v ) l after operation, set when overflow or underflow occurs. l in the case of bit instruction, bit6 of memory location is input to v-flag. l cleared by clrv instruction, but not set by any instruction. l branch condition flag of bvs, bvc. ? negative flag ( n ) l n-flag is set whenever the result of a data transfer or operation is negative (bit7 isset to ? 1 ? ). l in the case of bit instruction, bit7 of memory location is inputted to n-flag l no clear and set instruction. l branch condition flag of bpl, bmi.
gms 84512 / 84524 2 - 6 2.2 memory space the memory space of GMS84512/84524 is 64k byte, it is equipped with ram area, osd ram area, font rom area and program rom area. 2.2.1. ram area 0-page ( 0000 h - ~ 00ff h ) ram 192 bytes ( 0000 h ~ 00bf h ) and peripheral function register( 00c0 h ~ 00ff h ) 1-page ( 0100 h ~ 013f h ) ram 64 bytes ( 0100 h ~ 013f h ) and stack area 2-page ( 0200 h ~ 02d5 h ) osd ram 182 bytes ( 0200 h ~ 02d5 h ) 2.2.2. font rom area ( 2000 h ~ 3fff h ) 128 character osd font 2.2.3. program rom area approximately rom memory is 12 k bytes and it is domain of user program. the highest page(ff00 h ~ ffff h ) is called u- page and it is utilized domain as following. pcall area ( ff00 h ~ ffbf h ) domain of jumping at pcall instruction tcall vector area ( ffc0 h ~ ffdf h ) storage domain of vector address at tcall instruction. interrupt vector area ( ffe0 h ~ ffff h ) storage domin of interrupt vector address,inclusive reset
gms 84512 / 84524 2 - 7 memory map (GMS84512/84524 ) ffff h ffe0 h ffc0 h program rom no h/w no h/w interrupt vector area tcall vector area pcall area font rom ( 8 k bytes ) osd ram ( 182 bytes ) no h/w ram ( stack ) ( 64 bytes ) peripheral registers ram ( 192 bytes ) ff00 h a000 h d000 h 3fff h 2000 h 02d5 h 0200 h 013f h 0100 h 00ff h 00bf h 0000 h 0-page 1-page 2-page direct-page gms84524 ( 24k bytes ) GMS84512 ( 12k bytes ) u-page
gms 84512 / 84524 2 - 8 table 2.1. peripheralregister list address register name symbol r/w reset value page 7 6 5 4 3 2 1 0 00c0 h r0 port data register r0 r/w undefined 3 - 1 00c1 h r0 port i/o direction register r0dd w 0 0 0 0 0 0 0 0 3 - 1 00c2 h r1 port data register r1 r/w undefined 3 - 2 00c3 h r1 port i/o direction register r1dd w - 0 0 0 0 0 0 0 3 - 2 00c4 h r2 port data register r2 r/w undefined 3 - 4 00c5 h r2 port i/o direction register r2dd w 0 0 0 0 0 0 0 0 3 - 4 00c6 h r3 port data register r3 r/w undefined 3 - 6 00c7 h r3 port i/o direction register r3dd w 0 0 0 0 0 0 - - 3 - 6 00c8 h r4 port data register r4 r/w - - undefined 3 - 9 00c9 h r5 port data register r5 r/w - - - - undefined 3 - 10 00ca h port function selection register func w - - - 0 0 0 0 0 3 - 3 00cb h ext. interrupt edge selection register ieds w - - 0 0 0 0 0 0 3 - 39 00cc h operation mode register tmr w - - - - - 0 0 0 ?a 00ce h basic interval timer register bitr r undefined 3 - 16 clock control register ckctlr w - - 0 1 0 1 1 1 3 - 13 00cf h watch-dog timer register wdtr w - 0 1 1 1 1 1 1 3 - 17 00d0 h timer mode register0 tm0 r/w - 0 0 0 0 0 0 0 3 - 21 00d1 h timer mode register2 tm2 r/w - 0 0 0 0 0 0 0 3 - 21 00d2 h timer0 data register tdr0 r/w undefined 3 - 21 00d3 h timer1 data register tdr1 r/w undefined 3 - 21 00d4 h timer2 data register tdr2 r/w undefined 3 - 21 00d5 h timer3 data register tdr3 r/w undefined 3 - 21 00d6 h a/d comparator mode register cmr w *6 0 0 - 0 0 0 0 0 3 - 27 00d7 h a/d comp. channel selection register cis w - - - - - - 0 0 3 - 27 00d8 h serial i/o mode register siom r/w *0 - 0 0 0 0 0 0 1 3 - 29 00d9 h serial i/o data register sior r/w undefined 3 - 28 00da h pwm0 data register pwmr0 w - undefined 3 - 35 00db h pwm1 data register pwmr1 w - undefined 3 - 35 00dc h pwm2 data register pwmr2 w - undefined 3 - 35 00dd h pwm3 data register pwmr3 w - undefined 3 - 35
gms 84512 / 84524 2 - 9 address register name symbo l r/w reset value page 7 6 5 43 2 1 0 00de h pwm4 data register pwmr4 w - undefined 3 - 35 00df h pwm5 data register pwmr5 w - undefined 3 - 35 00e0 h pwm6 data register pwmr6 w - undefined 3 - 35 00e1 h pwm7 data register pwmr7 w - undefined 3 - 35 00e2 h pwm8 data register high pwm8h r/w undefined 3 - 36 00e3 h pwm8 data register low pwm8l r/w - - undefined 3 - 36 00e4 h pwm control register1 pwmcr1 r/w 0 0 0 00 0 0 0 3 - 37 00e5 h pwm control register2 pwmcr2 r/w - - - 00 0 0 0 3 - 37 00e6 h interrupt mode register imod r/w - - 0 00 0 0 0 4 - 4 00e8 h interrupt enable register low ienl r/w 0 0 0 0 0 - - - 4 - 3 00e9 h interrupt request flag register low irql r/w 0 0 0 0 0 - - - 4 - 4 00ea h interrupt enable register high ienh r/w 0 0 0 00 0 0 0 4 - 3 00eb h interrupt request flag register high irqh r/w 0 0 0 00 0 0 0 4 - 4 00ec h interrupt interval determination control register idcr r/w - - - - - 0 0 0 3 - 40 00ed h interrupt interval determination register idr r 0 0 0 00 0 0 0 3 - 38 00f0 h osd 1st line horizontal position register hdp1 w - - 0 00 0 0 0 3 - 47 00f1 h osd 2nd line horizontal position register hdp2 w - - 0 00 0 0 0 3 - 47 00f2 h osd 3rd line horizontal position register hdp3 w - - 0 00 0 0 0 3 - 47 00f3 h osd 1st line vertical position register vdp1 w - 0 0 00 0 0 0 3 - 47 00f4 h osd 2nd line vertical position register vdp2 w - 0 0 00 0 0 0 3 - 47 00f5 h osd 3rd line vertical position register vdp3 w - 0 0 00 0 0 0 3 - 47 00f6 h osd 1st line display mode, character size, smoothing function selection register dmss1 w - 0 0 00 0 0 0 3 - 44 00f7 h osd 2nd line display mode, character size, smoothing function selection register dmss2 w - 0 0 00 0 0 0 3 - 44 00f8 h osd 3rd line display mode, character size, smoothing function selection register dmss3 w - 0 0 00 0 0 0 3 - 44 00f9 h osd output and background control register osdcon1 w 0 0 0 00 0 0 0 3 - 48 00fa h i/o polarity control and osd oscillation control register osdcon2 w 0 0 0 00 0 0 0 3 - 48 00fc h osd ram ( 2 page ) accessable register pg2r** r/w - - - -- - - 0 3 - 43 ?? -: not used *0: read only for bit 0 *6: read only for bit 6 ?? write only register can not be accessed by bit manipulation instruction. ** : osd ram area (2-page) can be accessed by ldm,set1
gms 84512 / 84524 2 - 10 vector area ffc0 h ( l ) ffe0 h ( l ) ffc1 h ( h ) ffe1 h ( h ) ffc2 h ( l ) ffe2 h ( l ) ffc3 h ( h ) ffe3 h ( h ) ffc4 h ( l ) ffe4 h ( l ) ffc5 h ( h ) ffe5 h ( h ) ffc6 h ( l ) ffe6 h ( l ) ffc7 h ( h ) ffe7 h ( h ) ffc8 h ( l ) ffe8 h ( l ) ffc9 h ( h ) ffe9 h ( h ) ffca h ( l ) ffea h ( l ) ffcb h ( h ) ffeb h ( h ) ffcc h ( l ) ffec h ( l ) ffcd h ( h ) ffed h ( h ) ffce h ( l ) ffee h ( l ) ffcf h ( h ) ffef h ( h ) ffd0 h ( l ) fff0 h ( l ) ffd1 h ( h ) fff1 h ( h ) ffd2 h ( l ) fff2 h ( l ) ffd3 h ( h ) fff3 h ( h ) ffd4 h ( l ) fff4 h ( l ) ffd5 h ( h ) fff5 h ( h ) ffd6 h ( l ) fff6 h ( l ) ffd7 h ( h ) fff7 h ( h ) ffd8 h ( l ) fff8 h ( l ) ffd9 h ( h ) fff9 h ( h ) ffda h ( l ) fffa h ( l ) ffdb h ( h ) fffb h ( h ) ffdc h ( l ) fffc h ( l ) ffdd h ( h ) fffd h ( h ) ffde h ( l ) fffe h ( l ) ffdf h ( h ) ffff h ( h ) * this vector area is used in both brk and tcall 0 instruction not used serial i/o basic interval timer watch dog timer ext. int 3 timer 3 timer1 v-sync interrupt 1ms interrupt timer 2 timer 0 ext. int 2 ext. int1 on screen display not used reset tcall 15 tcall 14 tcall 13 tcall 12 tcall 11 tcall 10 tcall 9 tcall 8 tcall 7 tcall 6 tcall 5 tcall 4 tcall 3 tcall 2 tcall 1 tcall 0 *
GMS84512/84524 user ? s manual table of contents 1. overview 2. cpu 3. peripheral function 4. control function 5. support tool 6. appendix
gms 84512 / 84524 3- 1 3.1 port there are 6-ports in this device. you can use these ports an digital i/o or 2nd function i/o 3.1.1 r0 port 8-bit i/o port including direction register and port data register ( ioa type) l register structure and description register name symbol r/w address initial value r0 i/o direction register r0dd w 00c1 h 0000 0000 r0 port data register r0 r/w 00c0 h not initialized if output mode port is read, the read data is r0 register data. and if input mode port is read, the read data is r0 pin data. assign the direction of r0 port (r0dd0) is assigned to r00 port) 0 : input 1 : output <00c1 h > r0dd r0 port i/o direction register 7 r0dd7 6 r0dd6 5 r0dd5 4 r0dd4 3 r0dd3 2 r0dd2 1 r0dd1 0 r0dd0 w w w w w w w w initial value when reset [ 0000 0000 ] port r0 output data initial value when reset [not initialized ] <00c0 h > r0 r0 port data register 7 r07 6 r06 5 r05 4 r04 3 r03 2 r02 1 r01 0 r00 r/w r/w r/w r/w r/w r/w r/w r/w
gms 84512 / 84524 3 - 2 3.1.2 r1 port you can use the r17 port as input mode only, but others as input or output mode. selection mode pin name port selection 2nd function type 0 r10 r10 ( i/o ) r10 ( i/o ) ioa 1 r11 r11 ( i/o ) r11 ( i/o ) ioa 2 r12 r12 ( i/o ) r12 ( i/o ) ioa 3 r13 r13 ( i/o ) r13 ( i/o ) ioa 4 r14 r14 ( i/o ) r14 ( i/o ) ioa 5 r15/ cin1 r15 ( i/o ) cin1 ( i ) ioc 6 r16/ cin2 r16 ( i/o ) cin2 ( i ) ioc 7 r17/ cin0/ int3 r17 ( i ) cin0/ int3 ( i ) ic l register structure and description register name symbol r/w address initial value r1 i/o directin register r1dd w 00c3 h 0000 0000 r1 port data register r1 r/w 00c2 h not initialized a/d comp. input ch. selection register cis w 00d7 h ---- --00 port function selection register func w 00ca h ---0 0000 r1 port not used assign the direction of r1 port (r1dd0) is assigned to r10 port) 0 : input 1 : output <00c3 h > r1dd r1 port i/o direction register 7 - 6 r1dd6 5 r1dd5 4 r1dd4 3 r1dd3 2 r1dd2 1 r1dd1 0 r1dd0 - w w w w w w w initial value when reset [ -000 0000 ]
gms 84512 / 84524 3- 3 port selection cis1 cis0 channel r15/ cin1 r16/ cin 2 r17/ cin0/ int 3 r35/ sin/ cin3 0 0 channel 0 (cin0) r15 r16 cin0/ int3 r35/ sin 0 1 channel 1 (cin1) cin1 r16 r17/ cin0 r35/ sin 1 0 channel 2 (cin2) r15 cin2 r17/ cin0 r35/ sin 1 1 channel 3 (cin3) r15 r16 r17/ cin0 cin3 input data when read port r1 output data initial value when reset [ not initialized ] <00c2 h > r1 r1 port data register 7 - 6 r16 5 r15 4 r14 3 r13 2 r12 1 r11 0 r10 r r/w r/w r/w r/w r/w r/w r/w r27 / ec3 selection 0 : r27 ( i/o ) 1 : ec3 ( input ) r17 / int3 selection 0 : r17 ( input ) 1 : int3 ( input ) r26 / ec2 selection 0 : r26 ( i/o ) 1 : ec2 ( input ) r31/ int2 selection 0 : r31 ( input ) 1 : int2 ( input ) r30 / int1 selection 0 : r30 ( input ) 1 : int1 ( input ) <00ca h > func port function selection register 7 - 6 - 5 - 4 ec3s 3 ec2s 2 int3s 1 int2s 0 int1s - - - w w w w w initial value when mcu reset [ ---0 0 0 00 ] a/d comp. input channel selection initial value when reset [ ---- -- 00 ] <00d7 h > cis 7 - 6 - 5 - 4 - 3 - 2 - 1 cis1 0 cis0 - - - - - - w w analog input channel selection 00 : cin0 01 : cin1 10 : cin2 11 : cin3
gms 84512 / 84524 3 - 4 3.1.3 r2 port 8- bit i/o port selection mode pin name port selection 2nd functin type 0 r20 r20 ( i/o ) r20 ( i/o ) ioa 1 r21 r21 ( i/o ) r21 ( i/o ) ioa 2 r22 r22 ( i/o ) r22 ( i/o ) ioa 3 r23 r23 ( i/o ) r23 ( i/o ) ioa 4 r24 r24 ( i/o ) r24 ( i/o ) ioa 5 r25/ t2048 r25 ( i/o ) t2048 ( o ) iod 6 r26/ ec2 r26 ( i/o ) ec2 ( i ) iob 7 r27/ ec3 r27 ( i/o ) ec3 ( i ) iob l register structure and description register name symbol r/w address initial value r2 i/o direction register r2dd w 00c5 h 0000 0000 r2 port data register r2 r/w 00c4 h not initialized port function selection register func w 00ca h ---0 0000 pwm control register 2 pwmcr 2 r/w 00e5 h ---0 0000 r2 port assign the direction of r2 port r2dd is assigned to r20 port 0 : input 1 : output <00c5 h > r2dd r2 port i/o direction register 7 r2dd7 6 r2dd6 5 r2dd5 4 r2dd4 3 r2dd3 2 r2dd2 1 r2dd1 0 r2dd0 w w w w w w w w initial value when mcu reset [ 0000 0000 ]
gms 84512 / 84524 3- 5 port r2 output data initial value when mcu reset [ not initialized ] <00c4 h > r2 r2 port data register 7 r27 6 r26 5 r25 4 r24 3 r23 2 r02 1 r21 0 r20 r/w r/w r/w r/w r/w r/w r/w r/w r27 / ec3 selection 0 : r27 ( i/o ) 1 : ec3 ( input ) r17 / int3 selection 0 : r17 ( input ) 1 : int3 ( input ) r26 / ec2 selection 0 : r26 ( i/o ) 1 : ec2 ( input ) r31/ int2 selection 0 : r31 ( input ) 1 : int2 ( input ) r30 / int1 selection 0 : r30 ( input ) 1 : int1 ( input ) <00ca h > func port function selection register 7 - 6 - 5 - 4 ec3s 3 ec2s 2 int3s 1 int2s 0 int1s - - - w w w w w initial value when mcu reset ) [ --- 0 0 000 ] pwm output control register 2 initial value when mcu reset [ --- 0 0000 ] <00e5 h > pwmcr2 7 - 6 - 5 - 4 t2048 3 pol2 2 pol1 1 en7 0 en6 - - - r/w r/w r/w r/w r/w r25/ t2048 selection 0 : r25 1 :t2048 (output rectangular wave(t=2048us) 7-bit pwm output polarity 0 : positive polarity 1 : negative polarity 14-bit pwm output polarity 0 : positive poarity 1 : negative polarity r36/ pwm7 selection 0 : r36 1 : pwm7 r37/ pwm6 selection 0 : r37 1 : pwm6
gms 84512 / 84524 3 - 6 3 .1.4 r3 port you can use lower 2-bits(r31, r30) of r3 port as input mode only. but others as input or output mode selection mode pin name port selection 2nd function type 0 r30/ int1 r30 ( i ) int1 ( i ) ib 1 r31/ int2 r31 ( i ) int2 ( i ) ib 2 r32/ pwm8 r32 ( i/o ) pwm8 ( o ) iod 3 r33/ sout r33 ( i/o ) sout ( i/o ) iog 4 r34/ sclk r34 ( i/o ) sclk ( i/o ) iog 5 r35/ sin/ cin3 r35 ( i/o ) sin/ cin3 ( i ) ioe 6 r36/ pwm7 r36 ( i/o ) pwm7 ( o ) iof 7 r37/ pwm6 r37 ( i/o ) pwm6 ( o ) iof l register structure and description register name symbol r/w address initial value r3 i/o direction register r3dd w 00c7 h 0000 0000 r3 port data register r3 r/w 00c6 h not initialized port function selection register func w 00ca h ---0 0000 serial i/o mode register siom r/w 00d8 h -000 0001 pwm control register 1 pwmcr 1 r/w 00e4 h 0000 0000 pwm control regsiter 2 pwmcr 2 r/w 00e5 h ---0 0000 r3 port not used port r3 i/o direction register ( r3dd2 is assigned to r32 port ) 0 : input 1 : output <00c7 h > r3dd port r3 i/o direction register 7 r3dd7 6 r3dd6 5 r3dd5 4 r3dd4 3 r3dd3 2 r3dd2 1 - 0 - w w w w w w - - initial value when mcu reset [ 0000 00-- ]
gms 84512 / 84524 3- 7 input data when read port r3 output data initial value when mcu reset [ not initialized ] <00c6 h > r3 r3 port data register 7 r37 6 r36 5 r35 4 r34 3 r33 2 r32 1 - 0 - r/w r/w r/w r/w r/w r/w r r r27 / ec3 selection 0 : r27 ( i/o ) 1 : ec3 ( input ) r17 / int3 selection 0 : r17 ( input ) 1 : int3 ( input ) r26 / ec2 selection 0 : r26 ( i/o ) 1 : ec2 ( input ) r31/ int2 selection 0 : r31 ( input ) 1 : int2 ( input ) r30 / int1 selection 0 : r30 ( input ) 1 : int1 ( input ) <00ca h > func port function selection 7 - 6 - 5 - 4 ec3s 3 ec2s 2 int3s 1 int2s 0 int1s - - - w w w w w initial vlaue when mcu reset [ ---0 00 00 ] r42/ pwm3 selection 0 : r42 1 : pwm3 pwm control register 1 initial value when mcu reset [ 0000 00 0 0 ] <00e4 h > pwmcr1 7 en5 6 en4 5 en3 4 en2 3 en1 2 en0 1 en8 0 cnt r/w r/w r/w r/w r/w r/w r/w r/w r41/ pwm4 selection 0 : r41 1 : pwm4 r40/ pwm5 selection 0 : r40 1 : pwm5 r43/ pwm2 selection 0 : r43 1 : pwm2 r44/ pwm1 selection 0 : r44 1 : pwm1 r45/ pwm0 selection 0 : r45 1 : pwm0 r32/ pwm8 selection 0 : r32 1 : pwm8 14-bit / 7-bit pwm count start/stop 0 : count start 1 : count stop
gms 84512 / 84524 3 - 8 port selection sm1 sm0 function selection r33/ sout r34/ sclk r35/ sin/ cin3 * 0 0 - r33 r34 r35 0 1 send mode sout sclk r35 1 0 receive mode r33 sclk sin 1 1 - r33 r34 r35 r35 port will not operate, when cin3 is operating as a/d input port. pwm control register 2 initial value when mcu reset [ ---0 00 00 ] <00e5 h > pwmcr2 7 - 6 - 5 - 4 t2048 3 pol2 2 pol1 1 en7 0 en6 - - - r/w r/w r/w r/w r/w r25/ t2048 selection 0 : r25 1 :t2048 (output rectangular(t=2048ys)) 7-bit pwm output polarity 0 : positive polarity 1 : negative polarity 14-bit pwm output polarity 0 : positive polarity 1 : negative polarity r36/ pwm7 selection 0 : r36 1 : pwm7 r37/ pwm6 selection 0 : r37 1 : pwm6 serial i/o mode register initial value when mcu reset [ -0 00 0001 ] <00d8 h > siom 7 - 6 iosw 5 sm1 4 sm0 3 sck1 2 sck0 1 siost 0 siosf - r/w r/w r/w r/w r/w r/w r serial transmission clockselection 00 : ps3 ( 1 u s ) 01 : ps4 ( 2 us ) 10 : ps5 ( 4 us ) 11 : external clock serial operation mode 01 : receive mode (sclk, sout) 10 : send mode (sclk, sin) etc. : r33,r34,r35 selection serial transmission start 0 : invalid 1 : transmission start(reset after cycle ) erial transmission status flag 0 : in transmitting 1 : end of transmission serial input selection 0 : input via sin 1 : input via sout
gms 84512 / 84524 3- 9 3 .1.5 r4 port 6-bit output port. selection mode pin name port selection function selection type 0 r40/ pwm5 r40 ( o ) pwm5 ( o ) ob 1 r41/ pwm4 r41 ( o ) pwm4 ( o ) ob 2 r42/ pwm3 r42 ( o ) pwm3 ( o ) ob 3 r43/ pwm2 r43 ( o ) pwm2 ( o ) ob 4 r44/ pwm1 r44 ( o ) pwm1 ( o ) ob 5 r45/ pwm0 r45 ( o ) pwm0 ( o ) ob l register structure and description register name symbol r/w address initial value r4 port data register r4 r/w 00c8 h not initialized pwm control register pwmcr 1 r/w 00e4 h 0000 0000 r4 port port r4 output data initial value when mcu reset [ not initialized ] <00c8 h > r4 r4 port data register 7 - 6 - 5 r45 4 r44 3 r43 2 r42 1 r41 0 r40 - - r/w r/w r/w r/w r/w r/w not used r42/ pwm3 selection 0 : r42 1 : pwm3 pwm control register 1 initial value when mcu reset [ 0000 00 00 ] <00e4 h > pwmcr1 7 en5 6 en4 5 en3 4 en2 3 en1 2 en0 1 en8 0 cnt r/w r/w r/w r/w r/w r/w r/w r/w r41/ pwm4 selection 0 : r41 1 : pwm4 r40/ pwm5 selection 0 : r40 1 : pwm5 r43/ pwm2 selection 0 : r43 1 : pwm2 r44/ pwm1 selection 0 : r44 1 : pwm1 r45/ pwm0 selection 0 : r45 1 : pwm0 r32/ pwm8 selection 0 : r32 1 : pwm8 14-bit / 8-bit pwm count start/stop 0 : count start 1 : count stop
gms 84512 / 84524 3 - 10 3 .1.6 r5 port 4-bit output only port. selection mode pin name port selection 2nd function type 0 r50/ r r50 ( o ) r ( o ) oa 1 r51/ g r51 ( o ) g ( o ) oa 2 r52/ b r52 ( o ) b ( o ) oa 3 r53/ y r53 ( o ) y ( o ) oa l register structure and description register name sumbol r/w address initial value r5 port data register r5 r/w 00c9 h not initialized osd output/ b ackground control register osdcon1 w 00f9 h 0000 0000 r5 port port r5 output data initial value when mcu reset [ not initialized ] <00c9 h > r5 r5 port data register 7 - 6 - 5 - 4 - 3 r53 2 r52 1 r51 0 r50 - - - - r/w r/w r/w r/w not used background and edge color selecton initial value when mcr reset [ 0000 0000 ] <00f9 h > osdcon1 osd output & background control 7 oy 6 ob 5 og 4 or 3 o sd on 2 bb 1 bg 0 br w w w w w w w w r53/ y selection 0 : r53 1 : y r52/ b selection 0 : r52 1 : b r50/ r selection 0 : r50 1 : r r51/ g selection 0 : r51 1 : g osd output control 0 : disable 1 : enable
gms 84512 / 84524 3 - 11 3.2 clock generation circuit the clock generation circuit of GMS84512/84524 is consist of oscillation circuit for cpu clock, prescaler for peripheral clock and basic interval timer clock. basic interval timer for reference time, and water dog timer for detecting s/w overrun. 8 wdton p rescaler (11) enpck wdtcl to reset circuit ifwdt ifbit btcl peripheral circuit internal system clock c lock p ulse g enerator 7 0 b asic i nterval t imer(8) mux 2 1 ckctlr 0 osc circuit 8 11 6 5 0 5 0 wdt cl comparator 6 6 w atch d og t imer (6) 7 wdtr 5 fig.3.2.1 clock generation circuit block diagram internal data bus 6 3 4
gms 84512 / 84524 3 - 12 3.2.1 oscillation circuit the clock signal incoming from crystal oscillator or ceramic resonator via xin and xout, or from external clock via xin is supplied to clock pulse generator and prescaler internal system clock for cpu is made by clock pulse generator, and several peripheral clock is devided by prescaler clock generation circuit of crystal oscillator or ceramic resonator is shown in fig.3.2.2 ? clock generation circuit by crystal oscillator or ceramic resonator clock generator circuit by external clock fig. 3.2.2. clock generation circuit ? when stop mode, oscillation stops, xin pin is high-impedance, and xout pin is going to high level state. xin cin gnd cout xout xin external clock open xout
gms 84512 / 84524 3 - 13 3.2.2 prescaler prescaler is consisted of 11-bit binary counter, and input clock is supplied by oscillation circuit. frequency divided output from each bit of prescaler is used as peripheral clock. fig. 3.2.3 configuration of prescaler table 3.2.1 frequency-divided outputs of prescaler f ex ( ?) ps1 ps2 ps3 ps4 ps5 ps6 ps7 ps8 ps9 ps10 ps11 interval 4 ? 2 ? 1? 50 0 ? 25 0? 12 5 ? 62. 5 ? 31.2 5 ? 15.6 3 ? 7.1 8 ? 3.9 1? period 250 ns 50 0ns 1 u s 2 u s 4 u s 8 u s 1 6 u s 3 2 u s 6 4 u s 12 8us 25 6 u s interval 6 ? 3? 1.5 ? 750 ? 37 5 ? 187. 5 ? 93.7 5 ? 46.8 8 ? 23.4 4 ? 11.7 2 ? 5.8 6 period 166. 7ns 333. 3ns 666. 7ns 1. 3 u s 2. 7 u s 5. 3 u s 10. 7us 21. 3us 42. 7us 85. 3us 1 70. 7 u s l peripheral enpck f ex b.i.t. ps2 ps3 ps4 ps5 ps6 ps7 ps8 ps9 ps10 ps11 ps21 ps2 ps3 ps4 ps5 ps6 ps7 ps8 ps9 ps10 ps11 8 11 4 6 b.i.t. clear ( when writing ) 0 : b.i.t. free-run 1 : b.i.t. clear ( auto reset after 1-cycle ) b.i.t input clock selection (when writing) 000 : ps4 ( 2us) 100 : ps8 ( 3 2 us) 001 : ps5 ( 4 us) 101 : ps9 ( 6 4 us) 010 : ps6 ( 8 u s ) 1 10 : ps10 ( 12 8 us ) 011 : ps7 ( 1 6 us) 111 : ps11 ( 25 6 us) initial value when mcu reset ckctlr : [ --0 1 0111 ] clock control register 7 - 6 - 5 wdton 4 enpck 3 btcl 2 bts2 1 bts1 0 bts0 w w w w w w w w peripheral clock enable ( when writing ) 0 : peripheral clock stop 1 : peripheral clock supply wdt function control (when writing) 0 : 6bit timer 1 : watch-dog timer b.i.t. count value (when read) <00ce h > ckctlr
gms 84512 / 84524 3 - 14 peripheral hardware clock control function peripheral clock supplied from prescaler can be stopped by enpck. peripheral hardware clock control bit of ckctlr register.(however, ps11 cannot be stopped by enpck). 3.2.3 basic interval timer there is 8-bit binary counter is basic interval timer. it operates as following function. - reference time interval interrupt request as timer. - b.i.t. can be read ( note; the writing at same address overwrites the ckctlr.) - clock supply of w atch d og t imer. fig. 3.2.4 configuration of basic interval timer ps4 - - wdton enpck btcl bts2 bts1 bts0 ckctlr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 b.i.t. ps5 ps6 ps7 ps8 ps9 ps10 ps11 mux ifbit data bus data bus 8 6 same address when read, it can be read as counter value. when write, it can be write as control register.
gms 84512 / 84524 3 - 15 control of basic interval timer basic interval timer is free running timer, but it can be cleared by setting btcl ( bit 3 of clock control register). initial state (after reset) of btcl is ? 0 ? , and if it is set to ? 1 ? it is auto-cleared after 1 machine cycle. l input clock selection of basic interval timer and reference time interrupt interval input clock of basic interval timer is selected by bts2~bts0(bit2~0 of clock contro l register)among the prescaler outputs. reference time interval interrupt is generated by bit overflow. table 3.2.2 input clock selection of basic interval timer and reference time interrupt interval (@ 4 mhz) bts2 bts1 bts0 b.i.t. input clock period reference time interrupt period 0 0 0 ps4 ( 2us ) 512 us 0 0 1 ps5 ( 4us) 1,024 us 0 1 0 ps6 ( 8us) 2,048 us 0 1 1 ps7 ( 1 6us) 4,096 us 1 0 0 ps8 ( 3 2us) 8,192 us 1 0 1 ps9 ( 6 4us) 1 6 , 3 84 us 1 1 0 ps10 ( 12 8us ) 32,768 us 1 1 1 ps11 ( 25 6us ) 65,536 us b.i.t. input clock selection see table 3.3.2 b.i.t. clear ( when writing ) 0 : b.i.t. free-run 1 : b.i.t. clear ( auto cleared after 1 machine cycle ) initial value when mcu reset ckctlr : [ --01 0 111 ] clock control register 7 - 6 - 5 wdton 4 enpck 3 btcl 2 bts2 1 bts1 0 bts0 w w w w w w w w <00ce h > ckctlr b.i.t input clock selection ( when writing ) initial value when mcu reset ckctlr : [ --01 0 111 ] clock control register 7 - 6 - 5 wdton 4 enpck 3 btcl 2 bts2 1 bts1 0 bts0 w w w w w w w w b.i.t. count value (when read) <00ce h > ckctlr
gms 84512 / 84524 3 - 16 l reading of basic interval timer basic interval timer register can be read and interval up to 65ms can be measured (note : the writing at same address overwrites the ckctlr.) 3.2.4 watch dog timer w atch d og t imer is consist of 6-bit binary counter, 6-bit comparator and watch dog timer register(wdtr) ifwdt is generated when counter value equals to wdtr, it can be used as s/w interrupt or mcu reset (watch dog function) signal. initial value when mcu reset not initialized basic interval timer register 7 bit7 6 bit6 5 bit5 4 bit4 3 bit3 2 bit2 1 bit1 0 bit0 r r r r r r r r b.i.t.count value ( when read) <00ce h > bitr ifbit wdton to reset circuit data bus ifwdt clr 6 6-bit comparator fig. 3.2.4 configuration watch dog timer 0 wdt0 wdt1 wdt2 wdt3 wdt4 5 wdt5 6-bit counter wdtr 0 wdtr 0 wdtr 1 wdtr 2 wdtr 3 wdtr 4 wdtr 5 wdt cl 7
gms 84512 / 84524 3 - 17 l control of wdt wdtcan be used as 6-bit timer or watch dog timer according to wdton ( bit 5 of ckctlr). wdt is cleared by setting wdtcl (bit 6 wdtr) to ? 1 ? . < notice > 1: after wdton=1, maximum error of timer is are one of period of ifbit. 2: because 6-bit counter begin to count after mcu reset the watch dog timer should be enabled after clearing it. l interval of wdt interrupt interval of wdt interrupt is decided by basic interval timer interrupt an wdtr that is, interval of = ( wdtr value ) x ( ifbit interval ) . wdt control (when writing) 0 : 6-bit timer 1 : watch-dog timer initial value when mcu reset ckctlr : [ -- 0 1 0111 ] clock control register 7 - 6 - 5 wdton 4 enpck 3 btcl 2 bts2 1 bts1 0 bts0 w w w w w w w w <00ce h > ckctlr wdt clear 0 : wdt free-run 1 : wdt clear (auto reset after 1 cycle ) interval of wdt ifwdt period= ( wdtr value )x ( ifbit interval ) <00cf h > wdtr watch-dog timer register 7 - 6 wdtcl 5 wdtr 5 4 wdtr 4 3 wdtr 3 2 wdtr 2 1 wdtr 1 0 wdtr 0 - w w w w w w w initial value when mcu reset [ -011 1111 ]
gms 84512 / 84524 3 - 18 l selection of wdt clock and maximum interval of wdt interrupt input clock of wdt is ifbit, so wdt interval is decided by bts2~bts1. interval of wdt interrupt become maximum value. < notice > do not use wdtr=0 for mcu n ot to be reset state always. table 3.2.2 selection of wdt clock and maximum interval of wdt interrupt (@ 4 m h z ) bts2 bts1 bts0 b.i.t. input clock wdt input clock ifwdt max. interval 0 0 0 ps4 ( 2us ) 512 u s 32,256 u s 0 0 1 ps5 ( 4us ) 1,024 u s 64,512 u s 0 1 0 ps6 ( 8us ) 2,048 u s 129,024 u s 0 1 1 ps7 ( 1 6us ) 4,096 u s 258,048 u s 1 0 0 ps8 ( 3 2us ) 8,192 u s 516,096 u s 1 0 1 ps9 ( 6 4us ) 16,384 u s 1,032,192 u s 1 1 0 ps10 ( 12 8us ) 32,768 u s 2,064,384 u s 1 1 1 ps11 ( 25 6us ) 65,536 u s 4,128,768 u s
gms 84512 / 84524 3 - 19 3.3 timer timer of GMS84512/84524 is 8-bit binary counter is consisted of timer0(t0). timer1(t1), timer2(t2), timer(t3), timer data register(tdr0~tdr3). timer mode register(tm0, tm2) and control circuit. t0, t1 is each 8-bit interval timer and can be used as a 16-bit intrval timer. t2, t3 is each 8-bit interval timer/event counter and can be used as a 16-bit interval timer/event counter 3.3.1 operation mode of timer l operating mode of t0, t1 t0 t1 l 8-bit interval timer l 8-bit interval timer l 16-bit interval timer l operating mode oft2, t3 t2 t3 -. 8-bit interval timer -. 8-bit event counter -. 8-bit interval timer -. 8-bit event counter -. 16-bit interval timer -. 16-bit event counter when t2, t3 are used as event counter the relevant port mode register value should be assigned to select ec2 or ec3. when t2, t3 are used as event counter, tdr value should be initialized to ? ffh ? because timer count value is cleared if it equals to tdr value note) at the reset routine, tdr0 ~ tdr3 are should be initialized by software. (except 00h) r27 / ec3 selection 0 : r27 ( i/o ) 1 : ec3 ( input ) r26 / ec2 selection 0 : r26 ( i/o ) 1 : ec2 ( input ) <00ca h > func port function selection register 7 - 6 - 5 - 4 ec3s 3 ec2s 2 int3s 1 int2s 0 int1s - - - w w w w w initial value (when mcu reset [ --- 0 0 000 ]
gms 84512 / 84524 3 - 20 ck ps6 ps4 ps2 t0cn t1st t0st ps8 ps6 ps4 2 ps2 tdr0 data bus fig. 3.3.1 configuration timer0,timer1 16bit mode 16bit mode mux 8 tm0 7 1 0 3 2 5 4 - 6 tdr1 ift0 ift1 8 8 comparator 0 8 comparator 1 data reg. 1 data reg. 0 8 t 0 8 t 1 8 8 clear ck clear 1 mux 0 1 mux 0 mux 2 ck ps6 ps4 ec3 t2cn t3st t2st ps8 ps6 ps4 2 ec2 tdr2 tm2 data bus fig. 3.3.2 configuration of timer2,timer3 16bit mode 16bit mode mux 7 8 1 0 3 2 5 4 - 6 tdr3 ift2 ift3 8 8 comparator 2 8 comparator 3 data reg. 3 data reg. 2 8 t 2 8 t 3 8 8 clear ck clear 1 mux 0 1 mux 0 mux 2
gms 84512 / 84524 3 - 21 timer mode register 0 t1 input clock selection 00 : connection to t0 (16bit mode ) 01 : ps2 ( 50 0us ) 10 : ps4 ( 2us ) 11 : ps6 ( 8us ) t0 input clock selection 00 : ps2 ( 50 0us ) 01 : ps4 ( 2us ) 10 : ps6 ( 8us ) 11 : ps8 ( 3 2us ) initial value when mcu reset [ -000 0000 ] <00d0 h > tm0 7 - 6 t1st 5 t1sl1 4 t1sl0 3 t0st 2 t0cn 1 t0sl1 0 t0sl0 - r/w r/w r/w r/w r/w r/w r/w t0 start/stop control 0 : count stop 1 : counting start after clearing t0 t0 start/stop control 0 : count stop 1 : count start t1 start/stop control 0 : cout stop 1 : counting start after clearing t1 * don't care in 16bit mode timer mode register 2 t3 input clock selection 00 : connection to t2 ( 16bit mode ) 01 : input external clock source(ec3) 10 : ps2 ( 50 0us ) 11 : ps4 ( 2us ) t2 input clock selection 00 : input external clock source(ec2) 01 : ps2 ( 50 0us ) 10 : ps4 ( 2us ) 11 : ps6 ( 8u s ) initial value when mcu reset [ -000 0000 ] <00d1 h > tm2 7 - 6 t3st 5 t3sl1 4 t3sl0 3 t2st 2 t2cn 1 t2sl1 0 t2sl0 - r/w r/w r/w r/w r/w r/w r/w t2 start/stop control 0 : count stop 1 : counting start after clearing t2 t2 start/stop control 0 : count stop 1 : count start t3 start/stop control 0 : count stop 1 : counting start after clearing t3 * don't care in 16bit mode timer0 ~ timer3 data register initial value when mcu reset [ not initialized ] <00d2 h > tdr0 7 tdr0 7 6 tdr0 6 5 tdr0 5 4 tdr0 4 3 tdr0 3 2 tdr0 2 1 tdr0 1 0 tdr0 0 r/w r/w r/w r/w r/w r/w r/w r/w ( write) modulo data write of t0 modulo data write of t1 modulo data write of t2 modulo data write t3 ( read ) t0 count value read t1 count value read t2 count value read t3 count value read <00d3 h > tdr1 <00d4 h > tdr2 <00d5 h > tdr3
gms 84512 / 84524 3 - 22 table 3.3.1 timer resolutin and maximum count at f in =4mhz 8-bit timer mode 16-bit timer mode resolution( ck ) max.count resolution( ck ) max. count ps2 ( 0. 5? ) 128 ? ps2 ( 0. 5 ? ) 32,768 ? ps4 ( 2 ? ) 512 ? ps4 ( 2 ? ) 131,072 ? ps6 ( 8 ? ) 2,048 ? ps6 ( 8 ? ) 524,288 ? ps8 ( 3 2 ? ) 8,192 ? ps8 ( 3 2 ? ) 2,097,152 ? ps2 ( 0. 5 ? ) 128 ? ps2 ( 0. 5 ? ) 32,768 ? t2 ps4 ( 2 ? ) 512 ? ps4 ( 2 ? ) 131,072 ? ps6 ( 8 ? ) 2,048 ? ps6 ( 8 ? ) 524,288 ? ps2 ( 0. 5 ? ) 128 ? ( note ) t1 ps4 ( 2 ? ) 512 ? operation as upper 8-bit of t0 ps6 ( 8 ? ) 2,048 ? ps2 ( 0. 5 ? ) 128 ? ( note ) ps4 ( 2 ? ) 512 ? operation as upper 8-bit of t2 3.3.2 operation of timer0, timer1 t0 ( t1 ) is consisted of 8-bit binary up-counter. if t0 or t1 counter value become equal to tdr0(or tdr1) value, it is cleared to 00h, and interrupt request (ift0 or ift1) is generated. timer t0 t3 interval period interrupt interrupt interrupt match match match clear clear clear 00 h ift0 fig 3.3.3 operation of timer0 ,timer1 t0 value tdr0 value
gms 84512 / 84524 3 - 23 l any of the ps2, ps4, ps6 or ps8 can be selected as the clock source of t0 by bit1(t0sli) and bit0(t0sl0) of tm0. andy of the ps2, ps4, ps6 or overflow of t0 can be selected as the clock source of t1 by bit5(t1sl1) and bit4(t1sl0) of tm0. l the operation of t0, t1 is controlled by bit3(t0st), bit2(t0cn) and bit6(t1st) of tm0. t0cn controls count stop/start without clearing counter. t0st and t1st control count stop/start. in order to enable timer to count-up, t0cn, t0st and t1st should b ecome ? 1 ? . after clearing t0, t1 in order to count-up. t0st or t1st should become ? 0 ? for a moment and return to ? 1 ? . l the 16-bit interval timer is selected by assigning bit5(t1sl1) and bit4(t1sl0) to ? 0 ? . ) at 16-bit timer mode, ift0 interrupt only is valid. it is prefered to write to the tdr in non counting timer in order to protect undesirable interrupt. count count stop count stop ? 0 ? ? 1 ? start ? 0 ? ? 1 ? clear & start interrupt interrupt match match clear clear clear 00 h ift0 fig 3.3.4 start/ stop control of timer0 t0 value tdr0 value t0st counter t0cn
gms 84512 / 84524 3 - 24 3.3.2 operation of timer2, timer3 l t2 ( t3 ) is consisted of 8-bit binary up-counter. if t2(t3) counter value become equal to tdr2(tdr3) value, it is cleared to 00h and interrupt request (ift2 or ift3) is generated. l any of the ps2, ps4, ps6 or external event input can be selected as the clock source of t2 by bit1(t2sl1) and bit0(t2sl0) of tm0. any of the ps2, ps4 external event input or overflow of t2 can be selected as the clock source of t1 by bit5(t3sl1) and bit4(t3sl0) of tm0. if input clock is selected as external event input (ec2 or ec3), t2 and t3 operates as 8-bi t event counter. l the operation of t2, t2 is controlled by bit3(t2st), bit2(t2cn) and bit6(t3st) of tm2. controls count stop/start without clearing counter. t2st and t3st control count stop/start. order to enable timer to count-up t2cn, t2st a nd t3st should become ? 1 ? , after clearing t0,t1 in order to count-up. t2st or t3st should become ? 0 ? for a moment and return to ? 1 ? interval period interrupt interrupt interrupt match match match clear clear clear 00 h ift2 fig 3.3.5 operation of timer2 ( or timer3) t2 value tdr2 value
gms 84512 / 84524 3 - 25 l the 16-bit interval timer is selected by assigning bit5(t3sl1) and bit4(t3sl0) to ? 0 ? . at 16- bit timer mode, iift2 interrupt only is valid. it is prefered to write to the tdr in non- counting timer, in order to protect undesirable interrupt. if the input clock is selected among ps2, ps4 and ps6, t2 and t3 operate as 16-bit interval ti mer, while if ec2 operate as 16-bit event/counter. < notice > 1. on counting the reading value of tdr is counted value 2. 16-bit mode, when data are read i the middle of timer operation, the prior upper 8 bit data are read. next the lower 8-bit data are read, and then the upper 8 bit data are read once again. if the earlier read upper 8-bit data are matched with the later read upper 8 bit data, 16-bit data are read correctly. if not, caution should be taken in the selection of upper 8-bit data. ( example ) 1 ) upper 8 bit read 0a 0a 2 ) lower 8 bit read ff 01 3 ) upper 8 bit read 0b 0b ? ? 0aff 0b01 count count stop count stop ? 0 ? ? 1 ? start ? 0 ? ? 1 ? clear & start interrupt interrupt match match clear clear clear 00 h ift2 fig 3.3.6 start/ stop control of timer2 t2 value tdr2 value t2st counter t2cn
gms 84512 / 84524 3 - 26 3.4 a/d comparator a/d comparator has an 5-bit resolution, and input is possible up t o 4 channel. a/d comparator is consisted of analog input multiplexer, 5-bit d/a conversion circuit, sample & holder and control circuit fig.3.4.1 is a block diagram of a/d comparator 3.4.1 a/d comparator following produce is used. - write cis register to select analog input channel. - after writing cmr(adcm0~4) to select reference voltage, set aden(bit7 of cmr) to ? 1 ? to start a/d comparision.. < notice > cmrcan ? t be used with bit manipulation instruction and setting the reference voltage and starting a/d comparision can be used at same time.. - a/d comparision processing needs 16machine cycle(8us) - the result of comparision is stored in cor(bit6 of cmr). that is, if reference voltage>, cor=1 if , cor=0 data bus aden vref 6 7 2 fig. 3.4.1 block diagram of a/d comparator comparator cmr 5 adcm 3 analog input mu ltiple x er 5-bit d/a c. cin3 resister ladder aden cor - adcm 4 adcm 0 adcm 1 adcm 2 cis 1 0 5 2 - + cin2 cin1 cin0 output latch
gms 84512 / 84524 3 - 27 port selection cis1 cis0 function selection r15/ cin1 r16/ cin 2 r17/ cin0/ int 3 r35/ sin/ cin3 0 0 channel 0 (cin0) r15 r16 cin0/ int3 r35/ sin 0 1 channel 1 (cin1) cin1 r16 r17/ cin0 r35/ sin 1 0 channel 2 (cin2) r15 cin2 r17/ cin0 r35/ sin 1 1 channel 3 (cin3) r15 r16 r17/ cin0 cin3 l the calculation of reference voltage reference voltage ( vref ) = { 2 x ( value of adcm) + 1 } x vd d/ 64 a/d comp. input channel selection register initial value when mcu reset [ ---- -- 00 ] <00d7 h > cis 7 - 6 - 5 - 4 - 3 - 2 - 1 cis1 0 cis0 - - - - - - w w analog input channel selection 00 : cin0 01 : cin1 10 : cin2 11 : cin3 a/d comparator mode register initial value when mcu reset [ 00-0 0000 ] <00d6 h > cmr 7 aden 6 cor 5 - 4 adcm 4 3 adcm 3 2 adcm 2 1 adcm 1 0 adcm 0 w r - w w w w w reference voltage selection 00000 : vdd/ 64 10000 : 33vdd/ 64 00001 : 3vdd/ 6 4 10001 : 35vdd/ 64 00010 : 5vdd/ 64 10010 : 37vdd/ 64 | | 01111 : 31vdd/ 6 4 11111 : 63vdd/ 64 a/d comparison result 0 : input voltage reference voltage a/d comparision control 0 : a/d comparision stop 1 ; a/d comparision start
gms 84512 / 84524 3 - 28 3.5 serial i/o the serial i/o is 8-bit clock sychronous type and is consisted of serial i/o register, serial i/o mode register, clock sel ection circuit octal counter and control circuit. the sout pin is degined to input and output. so serial i/o interface can be operated with minimum two pin. 3.5.1 serial i/o data register serial i/o data register sior is a 8-bit shift register. first lsb is send or is received. initial value when mcu reset [ not initialized ] <00d9 h > sior 7 d7 6 d6 5 d5 4 d4 3 d3 2 d2 1 d1 0 d0 r/w r/w r/w r/w r/w r/w r/w r/w at transmittion sending data at sending receiving data at receiving fig. 3.5.1 block diagram of serial i/o sior 1 0 3 2 5 4 7 6 sclk octal counter control circuit data bus sm0 sm1 2 mux ps5 ps4 ps3 ifsio exclk 1 mux 0 sin sout data bus 8 6 6 7 0 siom sm0 sosf siost sck0 sck1 - iosw sm1
gms 84512 / 84 524 3 - 29 3.5.2 serial i/o mode register this register controls serial function. according to sck1, sck0 internal clock or external clock can be used. l port selection according to serial i/o mode port selection sm1 sm0 function selection r33/ sout r34/ sclk r35/ sin/ cin3 * 0 0 - r33 r34 r35 0 1 sending mode sout sclk r35 1 0 receiving mode r33 sclk sin 1 1 - r33 r34 r35 * if cin3 is used as a/d comparator input channel, r35 port do not operate as output.. l selection of serial input pin with the iosw when receiving mode, serial input pin is selected by iosw. that, if iosw=0, r35/sin is sel ected. if iosw=1, r33/sout serial i/o mode register initial value when mcu reset [ -0 00 0001 ] <00d6 h > siom 7 - 6 iosw 5 sm1 4 sm0 3 sck1 2 sck0 1 siost 0 siosf - r/w r/w r/w r/w r/w r/w r serial transmission clock selection 00 : ps3 ( 1us ) 01 : ps4 ( 2 u s ) 10 : ps5 ( 4 u s ) 11 : external clock serial operation mode 01 : sending mode (sclk, sout) 10 : receiving mode (sclk, sin) others : selection of r33,r34,r35 serial transmission start 0 : invalid 1 : start(after one sck, becomes ? 0 ? ) serial transmission status flag 0 : serial during transmission 1 : serial finished serial input selection 0 : via sin 1 : via sout
gms 84512 / 84524 3 - 30 3.5.3 data transmission/receving timing serial transmission is started by setting siost(bit1 siom) to : ? 1 ? . after one cycle of sck, siost is cleared automatically to ? 0 ? . serial output data from 8-bit shift register is output at folloing edge of sclk. and input data is latched at rising edge of sclek. when transmission clock is counted 8times, serial i/o counter is cleared as ? 0 ? . transmission clock is halted in ? h ? state and serial i/o interrupt (ifsio) occurs g. 3.5.4 data transmission/receiving method - select transmission/receiving mode when external clock is used, the f requency should be less than 1mh and recommanded duty is 50%. - when sending data to be send is written at sior. - set siost to ? 1 ? to start serial transmission. if both transmission mode selection and starting transmis sion is performed simultaneouslyit makes error. - ifsio is generated at completion and siosf is set to ? 1 ? . in sio interrupt service routine correct transmission should be tested. - when receiving, receiving data is acquired by reading the sior. d 7 d 6 d 5 d1 d 4 d 3 d 2 d0 d 7 d 6 d 5 d1 d 4 d 3 d 2 d0 input clock sclk latch output ifsio sin sout siost fig. 3.5.1 timing diagram of serial i/o
gms 84512 / 84 524 3 - 31 3.5.5 the method to test correct transmission with s/w 0 1 abnormal operation siosf ? fig. 3.5.4 serial method to teset transmission. note) se : interrupt enable regist low ienl ( bit3 ) sr : interrupt request flag regist low irql ( bit3 ) normal operation se = 0 write siom serial i/o interrupt service routine 1 0 overrun error sr ?
gms 84512 / 84524 3 - 32 3.6 pulse width modulation ( pwm ) the GMS84512/84524 is equipped with one 14-bit pwm(pwm8) and eight 7-bit pwm(pwm0~pw m7). the 14-bit resolution gives pwm8 the minium resolution bit width of 500ns(ps2=500ns, if xin=4mhz) and repeat period of 8,192us . each pwm0~pwm7 has a 7-bit resolution with min. resolution bit width of 8 us ( ps6 ) and repeat period of 1,024us . l pwm specification table ( @ xin =4mhz ) specification 14-bit pwm 7-bit pwm resolution 14 bits 7 bits input clock 0.5 us 8 u s 1 frame cycle 8,192 u s 1,024 u s pwmr 7 ? - pwmr0 7 1 0 3 2 5 4 - 6 pwm7 pwm6 pwm5 pwm4 pwm3 pwm2 pwm1 en0 data bus fig. 3.6.1 block diagram of 7-bit pwm & t2048 pwmcr2 5 1 0 3 2 - 4 - - pwmcr1 8 1 0 3 2 5 4 7 6 pwmr7 en7 pwmr1 pwmr2 pwmr3 pwmr4 pwmr5 pwmr6 en6 en5 en4 en3 en2 en1 match cntb pwm0 pol2 cntb 7-bit comparator ps6 7 pwmr0 7 t f/f 7-bit counter t2048e if 1ms t2048
gms 84512 / 84524 3 - 33 3.6.1 pwm8 (14-bit pwm ) when the pwm8 is used for output, first set the higher 8-bit of the pwm8h register, then the lower 6-bit of the pwm6 register. the 14-bit data of pwm8 can be compare with the 14-bit comparator after lower 6-bit data of pwm8 is transferred . data setting for pwm8(14-bit pwm) l the pwm output pulse period is consist with 64(=2 6 ) high level area which is consist with 256(=2 8 )low- level area. first, the basic pulse is made by the data of pwm8h, then the position of pulse as long as low level width(0. 5 us ) among 64 short pulse is determined by contents of pwm8l. table 3.6.1 bit sub-frame(short pulse) position as long as low level area pulse bit0 = ? 1 ? s32, 1 bit1 = ? 1 ? s16, s48 2 bit2 = ? 1 ? s8 , s24, s40, s56 4 bit3 = ? 1 ? s4 , s12, s20, s28, s36, s44, s52, s60 8 bit4 = ? 1 ? s2 , s6 , s10, s14, s18, s22, s26, s30, s34, s38, s42, s46, s50, s54, s58, s62 16 bit5 = ? 1 ? s1 , s3 , s5 , s7, s9, s11, s13, s15, s17, s19, s21, s23, s25, s27, s29, s31, s33, s35, s37, s39, s41, s43, s45, s47, s49, s51, s53, s55, s57, s59, s61, s63 32 en8 match cntb pwm8 pol1 cntb wpwm8l data bus fig. 3.6.2 block diagram of 14-bit pwm 14-bit comparator pwm8l 6 1 0 3 2 5 4 - - pwmcr2 5 1 0 3 2 - 4 - - 14 14 14-bit data register 14 14-bit counter ps2 pwmcr1 8 1 0 3 2 5 4 7 6 8 8 pwm8h 1 0 3 2 5 4 7 6
gms 84512 / 84524 3 - 34 basic pulse width ( 6 5 u s ) : sub-frame with added pulse pulse width = 65. 5 u s added pulse width( 0. 5 us ) pwm period ( 8,192 ) period of basic pulse ( 12 8 u s ) basic pulse width fig.3.6.3 example output of the 14-bit pwm ( polarity : positive ) added pulse number of added pulse ( pwm8l= 06 h ): 6 ( s8,s16,s24,s40,s48,s56 ) basic pulse width ( pwm8h= 82 h ): ( 130 ) x 0.5 = 65 u s initial value (at reset) [ undefined ] <00e2 h > pwm8h 7 d7 6 d6 5 d5 w 4 d4 3 d3 2 d2 1 d1 0 d0 initial value (at reset) [ undefined ] <00e3 h > pwm8l 7 - 6 - 5 d5 w 4 d4 3 d3 2 d2 1 d1 0 d0 13 1 12 0 11 0 10 0 9 0 8 0 7 1 6 0 5 0 4 0 3 0 2 1 1 1 0 0 s1 s0 s3 s2 s9 s8 s61 s63 s62 s57 s56 s49 s48 s25 s24 s41 s40 s17 s16
gms 84512 / 84524 3 - 35 3.6.2 pwm 0 ? - p wm7 ( 7-bit pwm ? ? 8 ch. ) each pwm0~pwm7 can be used for different pwm output by each 7-bit data register ( pwmr0~pwm7). the pwm pulse period is 1,02 4 and the width is (pwmr+1) ? ? t/128 . (0 pwmr0 7 6 | ? pwm0 d6 5 pwm0 d5 4 pwm0 d4 3 pwm0 d3 2 pwm0 d2 1 pwm0 d1 0 pwm0 d0 | ? w w w w w w w storage of each pwm data <00dc h > pwmr2 <00de h > pwmr4 <00e0 h > pwmr6 <00db h > pwmr1 <00dd h > pwmr3 <00df h > pwmr5 <00e1 h > pwmr7
gms 84512 / 84524 3 - 36 3.6.4 pwm8h, pwm8l register pwm register (pwm8h, pwm8l) are the data r egister to define 14bit pwm pulse width and it is enable r/w. they are not fixed at reset state. 3.6.5 the control of 14-bit pwm ? write upper data to pwm8h (definition of basic pulse width) write lower 6-bit data to pwm8l when data are written pwm8l, the 14-bit data of pwm8 is written to compare register so, even if you will change the upper 8-bit of output data, you will write 6bit data to pwm8l again. b ut when you will change the lower 6-bit of output data, you need not write the upper 8-bit to pwm8h again.. outpu t polarity is determined by pol1.( bit2 of pwm control register 2) default is positive polarity.(pol1=0) ? pwm8 port is selected by setting en8(bit1 of pwm ontrol register1) to ? 1 ? , so the wave of pwm is to be output. if cntb(bit6 of pwmcr1) is "0", counter is operating, on the contrary if it is "1" count stops. this have an effect on both of them.(14-bit pwm/7-bit p wm counter) initial value (at reset) [ undefined ] pwm8h , pwm8l data register <00e2 h > pwm8h 7 6 pwm8 h7 pwm8 h6 5 pwm8 h5 4 pwm8 h4 3 pwm8 h3 2 pwm8 h2 1 pwm8 h1 0 pwm8 h0 r/w r/w r/w r/w r/w r/w r/w r/w storage of 14-bit pwm upper 8-bit data when pwm8l is written it is loaded in upper 8-bit of 14-bit comparator, so the width of basic pulse are determined. when pwm8l is read, the contents(pwm8l) of comparator is read. initial value (at reset) [ undefined ] 7 6 ? a ? a 5 pwm8 l5 4 pwm8 l4 3 pwm8 l3 2 pwm8 l2 1 pwm8 l1 0 pwm8 l0 ? a ? a r/w r/w r/w r/w r/w r/w the number and position for added-pulse of 64 basic pulse are determined <00e3 h > pwm8l
gms 84512 / 84524 3 - 37 3.6.6 the control of 7-bit pwm ? write 7-bit data to each pwm data register (pwmr0~pwmr7). define output polarity by pol2 (bit3 of pwmcr2(pwm control register2)) positive polarity is determine by default. also this has effect an all 7bit pwm output if each pwm port is selected by setting en0~en7(bit2~bit7 of pwmcr1, bit1 and bit2 ofpwmcr2) to "1". if cntb(bit0 of pwmcr1) is "0", counter is operating, on the contrary if it is ? 1 ? counter stops. this has effect on all 14-bit pwm/7-bit pwm counter. r42/ pwm3 0 : r42 1 : pwm3 pwm control register 1 initial value (at reset) [ 0000 0000 ] <00e4 h > pwmcr1 7 en5 6 en4 5 en3 4 en2 3 en1 2 en0 1 en8 0 cntb r/w r/w r/w r/w r/w r/w r/w r/w select r41/ pwm4 0 : r41 1 : pwm4 select r40/ pwm5 0 : r40 1 : pwm5 select r43/ pwm 2 0 : r43 1 : pwm2 select r44/ pwm1 0 : r44 1 : pwm1 r45/ pwm0 0 : r45 1 : pwm0 stop/startr32/ pwm8 0 : r32 1 : pwm8 14-bit / 8-bit pwm count stop/start count start 1 : count stop pwm control register 2 initial value (at reset) [ ---0 0000 ] <00e5 h > pwmcr2 7 | ? 6 | ? 5 | ? 4 t2048 3 pol2 2 pol1 1 en7 0 en6 | ? | ? | ? r/w r/w r/w r/w r/w start r25/ t2048 0 : r25 1 :t2048 (period 2048 rectangular pulse output select) 7-bit pwm output polarity 0 : positive polarityy 1 : negative polarity 14-bit pwm output polartity 0 : positive polarity 1 : negative polarity select r36/ pwm7 0 : r36 1 : pwm7 select r37/ pwm6 0 : r37 1 : pwm6
gms 84512 / 84524 3 - 38 3.7. interrupt interval measurement circuit GMS84512/84524 is equipped with distinct edge of input signal for 2 channel external interrupt (in t1 , int2) and interrupt interval measurement circuit of evaluating distinct edge interval. interrupt interval measurement circuit is equipped with interrupt input multiplexer, 8bit binary up- counter measurement clock selection circuit, interrupt inter val storage circuit and interrupt interval measurement control register 3.7.1 operation of interrupt interval measurement circuit interrupt interval measurement circuit stores the count value of 8-bit up counter to idr(interrupt interval data register) by selected edge of external interrupt input. and then it may clear 8-bit up-counter, go on counting again. and the counter value of 8-bit up-counter is stored to idr by selected edge of seco nd external interrupt input. so, selected edge interval of external interrupt input is measured to ps8(3 2 ) or ps9(6 4 ). rising/falling edge of interrupt input signal is selected by ieds(external interrupt signal edge selection)and width or period of in put signal is measured by combination of selected edge. external interrupt input signal is selected by func(port function selection register) fig 3.7.2 and table 3.7.1 show interrupt input signal edge selection and measurement interval. 8 clear 3 2 idst 6 4 data bus fig. 3.7.1 configruation of interrupt interval measurement circuit idr 8 int1 8-bit up-counter idcr int2 ps9 ps8 2 0 7 ? a ? a ? a ? a ? a idst idck isel 3 1 mux 0 interrupt interval data register ck delay circuit 1 mux 0 data bus
gms 84512 / 84524 3 - 39 table 3.7.1 measurement interrupt interval and edge selection sym bol ied*h ied*l 1 0 ? 0 1 ? 1 1 e 1 1 r27 / ec3 selection 0 : r27 ( input, output ) 1 : ec3 ( input ) r17 / int3 selection 0 : r17 ( input ) 1 : int3 ( input ) r26 / ec2 selection 0 : r26 ( input, output ) 1 : ec2 ( input ) r31/ int2 selection 0 : r31 ( input ) 1 : int2 ( input ) r30 / int1 selection 0 : r30 ( input ) 1 : int1 ( input ) <00ca h > func port function selection register 7 | ? 6 | ? 5 | ? 4 ec3s 3 ec2s 2 int3s 1 int2s 0 int1s | ? | ? | ? w w w w w initial value (at reset) [ ---0 00 00 ] edge selection of external int input signal. 00 : no input selection 01 : falling edge selection 10 : rising edge selection 11 : both of edge all selection <00cb h > ieds ext. interrupt edge selection register 7 | ? 6 | ? 5 ied3h 4 ied3l 3 ied2h 2 ied2l 1 ied1h 0 ied1l | ? | ? w w w w w w initial value(at reset) [ --00 0000 ] period width of pulse int input signal ? ? e fig 3.7.2 the kind of interrupt interval
gms 84512 / 84524 3 - 40 3.7.2 interrupt interval measurement method the fol lowing is a interrupt interval measurement method. ? select interrupt input port to be used by writing data to func(00ca h ) to measure interrupt interval, select the edge of interrupt input signal by writing data to ieds( 00cb h ) control to write data to idcr (interrupt interval measurement control register) . when idst(bit0 fo idcr) is "1", counter is operating. if idck (bit1 of idcr) selecting measurement clock is "0", ps9(6 4 ) is selected, otherwise ps8(3 2 ) is selected. if isel(bit of idcr) selecting external interrupt input is "0", int1 is selected, otherwise int2 is selected. if using edge of interrupt input signal is to be input automatically the value of counter is stored to idr(00edh), after 1 machi ne cycle, counter is to be clear and go on count-up. so, interrupt interval is measured continuously. interval measurement clock selection 0 : 6 4 1 : 3 2 external int. input selection 0 : int1 1 : int2 counter start/stop control 0 : count stop 1 : after counter clear start count-up initial value(at reset) [ ---- -000 ] <00ec h > idcr interrupt interval determination control register 7 | ? 6 | ? 5 | ? 4 | ? 3 | ? 2 isel 1 idck 0 idst | ? | ? | ? | ? | ? r/w r/w r/w no use 33 h 1f h after 1 machine cycle start rising edge clear clear clear 00 h fig 3.7.3 the example of interrupt interval measurement 8-bit counter int input signal ? 33 h 1f h idr
gms 84512 / 84524 3 - 41 3.8 on screen display ( osd ) 3.8.1 osd overview the osd of GMS84512/84524 can display maxium 128 kinds of character or symbol to crt screen, basically GMS84512/84524 incorporates a 22 charac ters ? ? 3 lines c rt display control circuit. if osd interrupt is to be used, maxium 12 lines can be displayed. especially, GMS84512/84524 is equipped with smoothing function and color edge function. 3.8.2 feature of osd l osd clock : 4 ? ? - 8 ? l the nnmber of characte r : 128 characters ( include 2 test characters ) l display ability : 22 character ? ? 3 lines ( use osd interrupt : enable 12 lines ) l character size : 16 kinds ( every line unit ) l character color : 8 kinds ( every character unit ) l font configulation : 14 ? ? 18 dots l display position : horizontal 61 steps, vertical 128 step (every line unit) l display mode : character mode, background mode color edge mode, blanking mode ( every line unit ) l background size : domain of total screen, domain of line unit l background and edge color : 8 kinds l smoothing function l osd oscillator control function 3.8.3 configuration of osd the osd of GMS84512/84524 is equipped with osd oscillator, timing circuit, display position register (hdp1, hdp2, hdp3, vdp1, vdp2, vdp3) display mode register (dmss1, dmss2, dmss3), display control register (osdcon1, osdcon2), character rom storing 128 kinds of character font, display ram (22 cha racter ? ? 3 lines) storing font address and color data o f display character and output control circuit. fig 3.8.1 is a block of osd circuit of GMS84512/84524
gms 84512 / 84524 3 - 42 fig. 3.8.1 configuration of osd block bcol, py, pb, pg, pr osc, ph, pv osdon hsync vsync sm, mod 2 y b g r hd hps character color vs osd clock hs 2 vps dot clock 3 character address serial font data to port 14 14-bit shift register character rom ( 12 8 ? ? 1 4 ? ? 18 ) output control circuit 7 display ram ( 3 ? ? 2 2 ? ? 10 bit ) display position register display mode register data bus hdp1 hdp1 6 vertical position detection circuit horizontal position detection circuit 6 hdp1 hdp1 hdp1 7 hdp1 hdp1 7 dmss1 7 vdp1 7 ram address generation circuit timing generation circuit 5 row address generation circuit 7 3 vps data bus 5 3 8 4 osdcon2 osdcon1 control circuit vd osc2 osc1 3 5 3 8
gms 84512 / 84524 3 - 43 3.8.4 osd display ram ( 2-page, 0200 h ? - 02df h ) osd display ram is storing 3line s ? ? 22 characters of character address and color, gives data to character font rom and output control circuit in order to do osd output. when data are input, osd display ram separates character address and color and accesses twice. whe n data are output, data(10bits) are output once. if osd ram (2page) accessable register pg2r(00fch) is set "1" instruction of direct page addressing mode can be used to osd display ram. table 3.8.1 direct page access method g-flag = 1 pg2r = 0 pg2r = 1 0 page 1 page 2 page table 3.8.2 osd display ram address (2-page, 0200 h ? - 02df h ) 1st line 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 character 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 color 80 81 82 83 84 85 86 87 88 89 8a 8b 8c 8d 8e 8f 90 91 92 93 94 95 2nd line 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 character 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 30 31 32 33 34 35 color a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 aa a b a c ad ae af b0 b1 b2 b3 b4 b5 3rd line 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 character 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 53 54 55 color c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c a c b c c c d c e cf d0 d1 d2 d3 d4 d5 color data b g r black 0 0 0 red 0 0 1 green 0 1 0 yellow 0 1 1 blue 1 0 0 purpul 1 0 1 cyan 1 1 0 white 1 1 1 fig. 3.8.2 osd display ram and data configuration color 0 6 0 2 3rd line 2'st character character address ( 128 kinds) r g b c4 c5 c6 c0 c1 c2 c3 g-flag = 0
gms 84512 / 84524 3 - 44 3.8.5 osd display mode register ( dmss1, dmss2, dmss3 ) osd display mode register is register to control display character size, display mode, smoothing function. osd display mode register is every display line, so osd display mode is determined by line. l character size definition (every line unit) each character basic configuration is a 1 4 ? ? 18 dots. the dot size of vertical direction is determined by vs1, vs0(bit1, 0 of dmss) and the dot size of horizontal direction is determined by hs1, hs0(bit3, 2 of dmss). so, the size of display character is to be changable. table 3.8.3 character size definition hs1, hs0 vs1, vs0 00 1 ? ? 1 2 ? ? 1 3 ? ? 1 4 ? ? 1 01 1 ? ? 2 2 ? ? 2 3 ? ? 2 4 ? ? 2 10 1 ? ? 3 2 ? ? 3 3 ? ? 3 4 ? ? 3 11 1 ? ? 4 2 ? ? 4 3 ? ? 4 4 ? ? 4 osd mode register 7 6 5 4 3 2 1 0 | ? w w w w w w w | ? 1sm 1mod 1 1mod 0 1hs1 1hs0 1vs1 1vs0 initial value (at reset) [ -000 0000 ] dmss1 <00f6 h > dmss2 <00f7 h > dmss3 <00f8 h > character size definition 01 vs 00 11 10 2 1 00 1 1 4 1 3 1 2 2 01 1 2 4 2 3 2 2 3 10 1 3 4 3 3 3 2 4 11 1 4 4 4 3 4 smoothing function definition 0 : smoothing off 1 : smoothing on display mode definition 00 : blanking mode 01 : character mode 10 : color edge mode 11 : background mode 10 00 01 11
gms 84512 / 84524 3 - 45 l display mode definition (every line unit) display mode i s defined by mod1, mod0(bit5, 4 of dmss) and is blanking mode, character mode, color edge mode, background mode and so on. background domain is determined by bcol(bit6 of osdcon2). if bcol is "0" line domain is determined on the contrary, if bcol is "1" total screen is determined. notes : when bcol is "1" only background mode is enable (refer to fig 3,8,3) mode blanking mode character mode color edge mode background mode mod1,mod0 00 01 10 11 bcol=0 bcol=1 abcd abcd background color picture color edge character normal character abcd abcd abcd fig. 3.8.3 display mode abcd
gms 84512 / 84524 3 - 46 l smoothing function definition (every line unit) when the size of display character is over 2-times than normal size, smoothing function can smooth the rectangular part. smoothing function is defined by sm (bit 6 of dmss) (if sm is "1" function is on, otherwise function is off) fig 3.8.4 shows color edge function and smoothing function smoothing dot 2 2 original dot color edge dot f ig. 3.8.4 color edge function and smoothing function
gms 84512 / 84524 3 - 47 3.8.6 osd display position register( hdp 1 ? - hdp3, vdp 1 ? - vdp3) osd display position register defines horizontal, vertical position of screen every each display line. hdpi, vdpi define display position of i-line first character. (only i= 1,2,3) the value of hdpi is to be over four, the value of vdpi don't have to be included in domain of previous line. l horizontal display position ( hsi ) hsi = to ? ? { 4 ? ? ( hdpi ) ? 10 } [ to = osd clock period, i = 1, 2, 3 ] l vertical display position ( vsi ) vsi = 2 ? ? h ? ? ( vdpi ) [h = horizontal synchronous signal period, i = 1, 2, 3 ] each line horizontal position definition hsi = to ? ? { 4 ? ? ( hdpi) ? 10 } [ to = osd clock period, i = 1, 2, 3 ] osd horizontal position register 7 6 5 4 3 2 1 0 | ? | ? w w w w w w | ? | ? 1hp5 1hp4 1hp3 1hp2 1hp1 1hp0 initial value(at reset) [ --00 0000 ] hdp1 <00f0 h > hdp2 <00f1 h > hdp3 <00f2 h > each line vertical position definition vsi = 2 ? ? h ? ? ( vdpi ) [ h orizontal synchronous signal period,, i = 1, 2, 3 ] osd vertical position register 7 6 5 4 3 2 1 0 | ? w w w w w w w | ? 1vp6 1vp5 1vp4 1vp3 1vp2 1vp1 1vp0 initial value (at reset) [ -000 0000 ] vdp1 <00f3 h > vdp2 <00f4 h > vdp3 <00f5 h > hs2 ch 23 abcd efg hijk fig. 3 .8.5 crt screen and display position vs1 vs2 vs3 hs3 hs1 fuzzy on
gms 84512 / 84524 3 - 48 3.8.7 osd output control register( osdcon1, osdcon2 ) l osdcon1 ( 00f9 h ) osd output control register 1( osdcon1 )defines background and edge color (bb, bg, br) and is enable/disable osd output(osdon) and defines function of output port. (oy, ob, og, or) l osdcon2 ( 00fa h ) osd output control register 2 (osdcon2) defines the polarity of osd output(py,pb,pg,pr) and selects the polarity of input hd, vd(ph,pv) and defines background domain(bcol) and defines the type of osd oscillation (osc) . background and edge color selection initial value (at reset) [ 0000 0000 ] <00f9 h > osdcon1 osd output & background control register 7 oy 6 ob 5 og 4 or 3 o sd on 2 bb 1 bg 0 br w w w w w w w w r53/ y selection 0 : r53 1 : y r52/ b selection 0 : r52 1 : b osd output control 0 : disable 1 : enable r50/ r selection 0 : r50 1 : r r51/ g selecton 0 : r51 1 : g initial value (at reset) [ 0000 0000 ] <00fa h > osdcon2 osd i/o polarity & oscillation control register 7 osc 6 bcol 5 ph 4 pv 3 py 2 pb 1 pg 0 pr w w w w w w w w polarity control 0 : active low 1 : active high background domain determination 0 : line area 1 : full screen area oscillation type 0 : always (full screen) 1 : not always ( oscillation where only displayed) v-sync polarity h-sync polarity ypolarity b polarity g polarity r polarity
gms 84512 / 84524 3 - 49 3.8.8 multi line display the osd function of GMS84512/84524 is basically enable 3-line display, but if osd interrupt is used maximum up to 12 lines can be displayed. osd interrupt request occurs when osdon(bit3 of osdcon1) is "1" and each line display finishes, and osd interrupt happens when osd interrupt request occurs, at this time i-flag(bit2 of psw) and osde(bit7 of ienh(00ea h )) has to set "1". osd display allows multiple li nes(more than 3 lines) to be displayed on the screen by osd interrupt, each time one line is displayed and rewriting display ram data, display position register (hdpi, vdpi) and display mode register in the osd interrupt service routine for which display is terminated. l 6 line display occasion 1 ? st line display ram hdp1, vdp1, dmss1 2 ? nd line display ram hdp2, vdp2, dmss2 3 ? rd line display ram hdp3, vdp3, dmss3 3 ? rd line fig. 3.8.6 osd display method 2 ? nd line 1 ? st line 1 ? st line display ram hdp1, vdp1, dmss1 ? 1'st line dispaly ? ? load 4'th line data(contents, position, mode) to 1'st line ram and register. 2'nd line dispaly ? ? load 5'th line data(contents, position, mode) to 2'nd line ram and register 3'rd line display ? ? load 6'th line data(contents, position, mode) to 3'rd line ram and register 6'th ling dispaly ? 5'th line dispaly 4'th line dispaly
gms 84512 / 84524 3 - 50 otp / main otp / main ls b msb fig. 3.8.7 the example of character dot pattern 3.8.9 character rom the character rom of GMS84512/84524 stores 128 kinds of font dot pattern data. 36bytes of dot pattern data needs to display one character. fig 3.8.7 is a example of character dot pat tern, table 3.8.4 is a relation about character code and character dot pattern address. mds character code = 03h mds eprom 1 eprom 2 addr. data addr. data addr. data addr. data 060 h 00 h 2830 h 00 h 2030 h 00 h 060 h 00 h 061 h 00 h 2831 h 00 h 2031 h 00 h 061 h 00 h 062 h 30 h 2832 h 30 h 2032 h 06 h 062 h 06 h 063 h 18 h 2833 h 18 h 2033 h 0c h 063 h 0c h 064 h 0c h 2834 h 0c h 2034 h 18 h 064 h 18 h 065 h 06 h 2835 h 06 h 2035 h 30 h 065 h 30 h 066 h 03 h 2836 h 03 h 2036 h 60 h 066 h 60 h 067 h 01 h 2837 h 01 h 2037 h 40 h 067 h 40 h 068 h 01 h 2838 h 01 h 2038 h 40 h 068 h 40 h 069 h 03 h 2839 h 03 h 2039 h 60 h 069 h 60 h 06a h 06 h 283a h 06 h 203a h 30 h 06a h 30 h 06b h 0c h 283b h 0c h 203b h 18 h 06b h 18 h 06c h 18 h 283c h 18 h 203c h 0c h 06c h 0c h 06d h 30 h 283d h 30 h 203d h 06 h 06d h 06 h 06e h 00 h 283e h 00 h 203e h 00 h 06e h 00 h 06f h 00 h 283f h 00 h 203f h 00 h 06f h 00 h 070 h 00 h 3830 h 00 h 3030 h 00 h 070 h 00 h 071 h 00 h 3831 h 00 h 3031 h 00 h 071 h 00 h table 3.8.4 the relation of character code and dot pattern address character otp / main chip mds code upper 7 - bits lower 7 - bits upper 7-bit,lower 7- bit 00 h 2800 h ? - 280f h , 3800 h , 3801 h 2000 h ? - 200f h , 3000 h , 3001 h 000 h ? - 011 h 01 h 2810 h ? - 281f h , 3810 h , 3811 h 2010 h ? - 201f h , 3010 h , 3011 h 020 h ? - 031 h 02 h 2820 h ? - 282f h , 3820 h , 3821 h 2020 h ? - 202f h , 3020 h , 3021 h 040 h ~ 0 5 1 h 03 h 2830 h ? - 283f h , 3830 h , 3831 h 2030 h ? - 203f h , 3030 h , 3031 h 060 h ? - 071 h xx h 7e h * 2fe0 h ? - 2fef h , 3fe0 h , 3fe1 h 27e0 h ? - 27ef h , 37e0 h , 37e1 h fc0 h ? - fd1 h 7f h * 2ff0 h ? - 2fff h , 3ff0 h , 3ff1 h 27f0 h ? - 27ff h , 37f0 h , 37f1 h fe0 h ? - ff1 h * these addresses are reserved for test ( user not available ) ( 20 h * xx h + 00 h ) ? - ( 20 h * xx h + 11 h ) ( 2000 h + xx0 h ) ? - (2000 h + xxf h ) ( 3000 h + xx0 h ) , (3000 h + xx1 h ) ( 2800 h + xx0 h ) ? - (2800 h + xxf h ) ( 3800 h + xx0 h ) , (3800 h + xx1 h )
GMS84512/84524 user ? s manual table of contents 1. overview 2. cpu 3. peripheral function 4. control function 5. support tool 6. appendix
gms 84512 / 84524 4 - 1 4.1 interrupts GMS84512/84524 has the following function to process interrupt request from the peripheral and external interr upt pin. l interrupt source : 14 l interrupt vector : 14 l multi interrupt possible. l programmable interrupt mode ? hardware priority mode software selection mode l r/w of interrupt request flag is possible and in interrupt accept, automalically resetted. 4.1.1 interrupt circuit configuration and kinds GMS84512/84524 interrupt circuits is consist of interrupt enable register (ienh,ienl), interrupt request register (irqh,irql), priority circuit and selecting circuit. configuration of interrupt circuit is shown in fig. 4.1.1 the interrupt sources are external interrupt source(int1, int2, int3, v-sync), peripheral function source(osd,t0,t1,t2,t3,1ms,wdt,bit,serial i/o) and software interrupt source(brk). in the case of reset input(reset), the program execution at the start address located in vector table address like general interrupt. the classification of interrupt source is shown in table 4.1.1.
gms 84512 / 84524 4 - 2 13 irql irqh 3 7 7 0 reset ifosd fig. 4.1.1 interrupt function block diagram data bus imod 6 i-flag brk to cpu standby mode release priority control int1r osdr ienh 8 1 0 3 2 5 4 7 6 8 4 1 0 3 2 5 4 ? ? ? ? t0r int2r 1msr t2r t1r vsync wdtr int3r sr bitr t3r ienl 5 ? ? ? ? 3 ? ? 5 4 7 6 data bus 5 int1 int2 ift0 ift2 if1m ifvsync ift1 ift3 int3 ifwdt if bit ifs 8 interrupt vector address gen.
gms 84512 / 84524 4 - 3 table 4.1.1 interrupt request source type mask priority interrupt request source vector h vector l non maskable 1 rst reset pin ffff h fffe h 2 osd on screen display fffb h fffa h 3 int1r external interrupt 1 fff9 h fff8 h 4 int2r external interrupt 2 fff7 h fff6 h 5 t0r timer 0 fff5 h fff4 h 6 t2r timer 2 fff3 h fff2 h hardware mask 7 1ms 1 a interrupt fff1 h fff0 h interrupt enable 8 vsync v-sync interrupt ffef h ffee h 9 t1r timer 1 ffed h ffec h 10 t3r timer 3 ffeb h ffea h 11 int3r external interrupt 3 ffe9 h ffe8 h 12 wdtr watch dog timer ffe7 h ffe6 h 13 bitr basic interval timer ffe5 h ffe4 h 14 sr serial i/o ffe3 h ffe2 h s/w interrupt non maskable ? a brk break instruction ffdf h ffde h 4.1.2 interrupt control l to process interrupt, set the interrupt master enable flag i-flag(3'rd bit of psw). when i-flag="0" all interrupts are disable except reset and s/w interrupt. l interrupt enable register ( ienh, ienl ) includes interrupt enable bits of each interrup t ` source, and interrupt is accepted when the interrupt enable bit and the interrupt request bit are both "1". interrupt masking flag 0 : interrupt disable 1 : interrupt enable initial value (at reset) [ 0000 0000 ] <00ea h > ienh interrupt enable register h, l 7 osde 6 int1e 5 int2e 4 t0e 3 t2e 2 1me 1 vsync e 0 t1e r/w r/w r/w r/w r/w r/w r/w r/w initial value (at reset) [ 0000 0--- ] <00e8 h > ienl 7 t3e 6 int3e 5 wdte 4 bite 3 se 2 | ? 1 | ? 0 | ? r/w r/w r/w r/w r/w | ? | ? | ?
gms 84512 / 84524 4 - 4 l interrupt request flag register ( irqh, irql ) when interupt occurs, interrupt request flag is set. the accepted interrupt request flag is automatically cleared by interrupt process cycle. as long as the interrupt request flag which is set to "1" is not clear ed by program, it maintains '1" until interrupt is accepted. interrupt request flag register ( irqh, irql ) is read/ write register. so, it is possible to be checked and changed by program. l interrupt mode register ( imod ) interrupt mode register determines interrupt priority which can be selected by hardware or program. interrupt request flag 0 : disable 1 : enable initial value (at reset) [ 0000 0000 ] <00eb h > irqh interrupt request flag register h, l 7 osdr 6 int1r 5 int2r 4 t0r 3 t2r 2 1mr 1 vsync r 0 t1r r/w r/w r/w r/w r/w r/w r/w r/w initial value (at reset) [ 0000 0--- ] <00e9 h > irql 7 t3r 6 int3r 5 wdtr 4 bitr 3 sr 2 | ? 1 | ? 0 | ? r/w r/w r/w r/w r/w | ? | ? | ? interrupt mode definition 00 : mode 0 (priority by h/w) 01 : mode 1(definition by ip 3 ? - ip0) 1- : inhibit interrupt interrupt definition selection 0000 : | ? 1000 : timer 1 0001 : osd 1001 : timer 3 0010 : int1 1010 : int3 0011 : int2 1011 : wdt 0100 : timer 0 1100 : b.i.t. 0101 : timer 2 1101 : serial 0110 : 102 4 1110 : | ? 0111 : v-sync 1111 : | ? initial value (at reset) [ undefined ] <00e6 h > imod interrupt mode register 7 | ? 6 | ? 5 im1 4 im0 3 ip3 2 ip2 1 ip1 0 ip0 | ? | ? r/w r/w r/w r/w r/w r/w
gms 84512 / 84524 4 - 5 l interrupt mode mode 0 ( priority by h/ w ) osd r ? int1 r ? int2 r ? t0 r ? t2 r ? 1m r ? vsync r ? t1 r ? t3 r ? int3 r ? wdt r ? bit r ? sr ? mode 1 (selection by i p3 ? - ip0) table 4.1.2 selection of interrupt by ip3 ? - i p0 ip 3 ip 2 ip 1 ip0 selection interrupt 0 0 0 0 ? a 0 0 0 1 osdr on screen display 0 0 1 0 int1r external interrupt 1 0 0 1 1 int2r external interrupt 2 0 1 0 0 t0r timer 0 0 1 0 1 t2r timer 2 0 1 1 0 1msr 1 a interrupt 0 1 1 1 vsyncr external v-sync interrupt 1 0 0 0 t1r timer 1 1 0 0 1 t3r timer 3 1 0 1 0 int3r external interrupt 3 1 0 1 1 wdtr watch dog timer 1 1 0 0 bitr basic interval timer 1 1 0 1 sr serial i/o 1 1 1 0 ? a 1 1 1 1 ? a l interrupt accept timing 1 cycles 0 ? - 12 cycles 8 cycles system clock instruction fetch fig. 4.1.2 interrupt accept timing interrupt overhead : 9 ? - 21 cycles int. request sampling interru pt process step interru ptroutine a command before interrupt
gms 84512 / 84524 4 - 6 l the vlaid timing after executing interrupt control flag i-flag is valid, after ei, di executed ? ienh, ienl register is valid after next instruction 4.1.3 interrupt sequence when interrupt is accepted, the execu tion program is stopped, a certain of interrupt processing step is passed, and interrupt sevice routine is started. by last instruction of interrupt service routine(reti) return to original program. l interrupt process sequence v.l system clock fig. 4.1.3 interrupt process step timing instruction fetch sp-2 new pc v.h v.l sp-1 pc sp address bus psw opcode adh adl pcl v.l , v.h is vector address, adl, adh is start address of interrupt service routine as vector contents interrupt process step interrupt service routine not used pch data bus internal read internal write interrupt service routine i-flag = ? 0 ? (b-flag= ? 1 ? at brk) psw stacking s p ? ? sp -1 pcl stacking s p ? ? sp -1 pch stacking s p ? ? sp -1
gms 84512 / 84524 4 - 7 4.1.4 software interrupt software interrupt is interrupted by brk instr uction. in interrupt processing step i-flag is cleared. b-flag is setted. interrupt vector of brk instruction is shared with the vector of table call 0, when both instruction of brk and tcall 0 are used, each processing routine is executable throug h looking at the contents at b-flag. there is no instruction to reset b-flag directly. 4.1.4 multiple interrupt if there is an interrupt, interrupt enable flag is automalically resetted entering the interrup t service routine. after then, no interrupt is accepted. if ei instruction is executed, mask enable bit becomes "1", and each enable bit can accept the interrupt as a reply to 1's interrupt request. if multiple of interrupt request occurs at same time , the one with a higher priority is accepted and the other with lower priority are retained. v n psw after brk instruction b g i h c z ? a ? a 1 ? a 0 ? a ? a ? a 0 brk or tcall0 1 tcall 0 routine fig. 4.1.4 execution of brk/ tcall0 brk interrupt routine rtn b-flag ? rtni
gms 84512 / 84524 4 - 8 when multiple interrupt is accepted, it is possible to change interrupt accept mode. l case of multiple interrupt at hardware priority accept mode(mode0) l case of multiple interrupt nest h/w priority accept mode (mode0) and s/w selection accept mode(mode1) ei ei ei main program ( mode 0 ) 1 ? st int. routine ( mode 0 ) 2 ? nd int. routine ( mode 0 ) 3 ? rd int. routine interrupt interrupt interrupt ei ei ei main program ( mode 0 ) 1 ? st int. routine ( mode 0 ) 2 ? nd int. routine ( mode 1 ) 3 ? rd int. routine interrupt interrupt interrupt reload imod stacking imod change mode
gms 84512 / 84524 4 - 9 4.2. standby function to save the consuming power of device,GMS84512/84524 has stop mode. in this mode,the execution of program stop. stop mode can be entered by stop instruction.
gms 84512 / 84524 4 - 10 table 4.2.1 at stop mode device operation state. peripheral function stop mode oscillator ? ? cpu clock ? ? ram, register retain i/o port retain prescaler ? ? basic interval timer ? ? serial i/o operation( external clock selection) wdt, timer, a/d comp., pwm, osd, interrupt interval mesurment circuit ? ? halt stop ifbit cpu clock release signal from interrupt circuit reset clock pulse gen. clr mux prescaler clr fig. 4.2.1 stop mode circuit diagram r q s q overflow detection basic interval timer clr r q s q osc. circuit
gms 84512 / 84524 4 - 11 4.2.1 stop mode stop mode can be entered by stop instruction during program execution. in stop mode, oscillator is stopped to make all clocks stop, which leads to the mode requring much less power consumption. all register and ram data are preserved. 4.2.2 stop mode release release of stop mode is done by reset input or interrupt. when there is a release signal of stop mode, the instruction execution is started after stabilization oscillation time set by program. after releasing stop mode, instruction execution is different by i-flag(bit 2 of psw) if i-flag = ? 1 ? entered interrupt service routine, if i-flag = ? 0 ? execute program from next instruction of stop instruction. table 4.2.1 stop mode release release factor release method stop reset by reset pin=low level, and device is initialzed. int1,int2 int3, v-sync in the state of enable flag=1 corrosponding to each interrupt at the edge. serial i/o ( ifsio ) when se="1" and serial i/o is executing by external clock, interrupt occurs by serial i/o operation completed l release timing of stop mode system clock release signal by interrupt stop stabilization oscillation time stop mode determined by program . reset stabilization oscillation time + 8 cycles ?
gms 84512 / 84524 4 - 12 when release the stop mode, to secure oscillation stabilization time,we use a b.i.t. so before execution stop instruction, we must select s uitable bit clock for oscillation stabillization time. otherwise, it is possible to release by only reset input. l because stop mode is released by interrupt, even if both of interrupt enable bit(ie) and interrupt request flag is "1", stop mode can n ot be executed. fig. 4.2.2 stop mode releasing flow 0 1 next command execution interrupt service routine i-flag ? 0 1 stop mode release interrupt request ie ? stop mode stop command
gms 84512 / 84524 4 - 13 4.3. reset function to reset the device, maintain the reset="l" at least 8 machine cycle after power supplying and oscillation stabilization. reset terminal is organized as schmitt input. table 4.3.1 is, at reset , initial value of each register, if initial value is undefined it is needed initialize by a s/w. fig 4.3.1 is timing of reset operation (simular as interrupt instruction) l clock control register opcode system clock fig. 4.1.1 reset operation timing instruction fetch ? start ffff fffe ? ? ? address bus fe ? adh adl ? fffe h , is vector address and adl, adh is start address of main program as vector contents reset process step main program ? ? data bus internal read reset b.i.t. clear ( initial value) 0 : b.i.t. free-run b.i.t input clock selection (initial value) 111 : ps11 ( 25 6 ) initial value (at reset) ckctlr : [ --01 0111 ] bitr : [ undefined ] clock control register 7 | ? 6 | ? 5 wdton 4 enpck 3 btcl 2 bts2 1 bts1 0 bts0 w w w w w w w w peripheral clock enable(initial value) 1 : peripheral clock supply wdt function control( initial value ) 0 : 6bit timer b.i.t. value ( read ) <00ce h > ckctlr
gms 84512 / 84524 4 - 14 table 4.3.1 initial state of each register at reset block symbol address register name r/w initial value page 76 5 43 2 1 0 a ? a a - register ? a undefined 2 - 2 x ? a x- register ? a undefined 2 - 2 cpu y ? a y - register ? a undefined 2 - 2 psw ? a program status word ? a 00 0 00 0 0 0 2 - 3 pc ? a program counter ? a undefined 2 - 3 sp ? a stack pointer ? a undefined 2 - 2 r0 00c0 h r0 port data register r/w undefined 3 - 1 r0dd 00c1 h r0 port i/o direction register w 00 0 00 0 0 0 3 - 1 r1 00c2 h r1 port data register r/w undefined 3 - 2 r1dd 00c3 h r1 port i/o direction register w 00 0 00 0 0 0 3 - 2 r2 00c4 h r2 port data register r/w undefined 3 - 4 port r2dd 00c5 h r2 port i/o direction register w 00 0 00 0 0 0 3 - 4 r3 00c6 h r3 port data register r/w undefined 3 - 6 r3dd 00c7 h r3 port i/o direction register w 00 0 00 0 - - 3 - 6 r4 00c8 h r4 port data register r/ w - - undefined 3 - 9 r5 00c9 h r5 port data register r/ w -- - - undefined 3 - 10 func 00ca h port function selection register w -- - 00 0 0 0 3 - -3 ieds 00cb h external interupt edge selection register w - - 0 00 0 0 0 3 - 39 bitr 00ce h basic interval timer register r undefined 3 - 16 ckctlr clock control register w - - 0 10 1 1 1 3 - 13 wdtr 00cf h w atch dog timer register w - 0 1 11 1 1 1 3 - 17 tm0 00d0 h timer mode register0 r/ w - 0 0 00 0 0 0 3 - 21 timer tm2 00d1 h timer mode register2 r/ w - 0 0 00 0 0 0 3 - 21 tdr0 00d2 h timer0 data register r/w undefined 3 -21 tdr1 00d3 h timer1 data register r/w undefined 3 - 21 tdr2 00d4 h timer2 data register r/w undefined 3 - 21 tdr3 00d5 h timer3 data register r/w undefined 3 - 21 a/d comp. cmr 00d6 h a/d comparator mode register w* 6 0 0 - 00 0 0 0 3 - 27 cis 00d7 h a/d comparator channel selection register w -- - -- - 0 0 3 - 27 siom 00d8 h serial i/o mode register r/w *0 - 0 0 00 0 0 1 3 - 29 sior 00d9 h serial i/o data register r/w undefined 3 - 28 imod 00e6 h interrup mode register r/ w - - 0 00 0 0 0 4 - 4 ienl 00e8 h interrupt enable register low r/ w 00 0 0 0 - - - 4 - 3 interrupt irql 00e9 h interrupt request flag register low r/ w 00 0 0 0 - - - 4 - 4 ienh 00ea h interrupt enable register high r/ w 00 0 00 0 0 0 4 - 3 irqh 00eb h interrupt request flag register high r/ w 00 0 00 0 0 0 4 - 4 ieds 00cb h external interupt edge selection register w - - 000 0 0 0 3 - 39 interrupt idcr 00ec h interrupt interval determination control register r/ w -- - - - 0 0 0 3 - 40 interval d. idr 00ed h interrupt interval determination register r 00 0 00 0 0 0 3 - 38 serial i/o
gms 84512 / 84524 4 - 15 table 4.3.1 initial state of each register at reset block symbol address register name r/w initial value page 76 5 43 2 1 0 pwm0 00da h pwm0 data register w - undefined 3 - 35 pwm1 00db h pwm1 data register w - undefined 3 - 35 pwm2 00dc h pwm2 data register w - undefined 3 - 35 pwm3 00dd h pwm3 data register w - undefined 3 - 35 pwm4 00de h pwm4 data register w - undefined 3 - 35 pwm pwm5 00df h pwm5 data register w - undefined 3 - 35 pwm6 00e0 h pwm6 data register w - undefined 3 - 35 pwm7 00e1 h pwm7 data register w - undefined 3 - 35 pwm8h 00e2 h pwm8 data register high r/w undefined 3 - 36 pwm8l 00e3 h pwm8 data register low r/ w - - undefined 3 - 36 pwmcr1 00e4 h pwm control register1 r/ w 00 0 00 0 0 0 3 - 37 pwmcr2 00e5 h pwm control register2 r/ w -- - 00 0 0 0 3 - 37 hdp1 00f0 h osd 1st line horizontal position register w - - 0 00 0 0 0 3 - 47 hdp2 00f1 h osd 2nd line horizontal position register w - - 0 00 0 0 0 3 - 47 hdp3 00f2 h osd 3rd line horizontal position register w - - 0 00 0 0 0 3 - 47 vdp1 00f3 h osd 1st line vertical position register w - 0 0 00 0 0 0 3 - 47 vdp2 00f4 h osd 2nd line vertical position register w - 0 0 00 0 0 0 3 - 47 vdp3 00f5 h osd 3rd line vertical position register w - 0 0 00 0 0 0 3 - 47 osd dmss1 00f6 h osd 1st line display mode, character size, smoothing function selection register w - 0 0 00 0 0 0 3 - 44 dmss2 00f7 h osd 2nd line display mode, character size, smoothing function selection register w - 0 0 00 0 0 0 3 - 44 dmss3 00f8 h osd 3rd line display mode, character size, smoothing function selection register w - 0 0 00 0 0 0 3 - 44 osdcon1 00f9 h osd output and background control register w 00 0 00 0 0 0 3 - 48 osdcon2 00fa h osd i/o polarity control and osd oscilllation control register w 0 0 000 0 0 0 3 - 48 pg2r 00fc h osd ram ( 2 page ) accessable register r/ w -- - -- - - 0 3 - 43 ? ? -: not use , *0: bit 0 is read only , *6: bit 6 is read only.
GMS84512/84524 user ? s manual table of contents 1. overview 2. cpu 3. peripheral function 4. control function 5. support tool 6. appendix
gms 84512 / 84524 5 - 1 5.1 emulator { ref. gms800 series mds manual } the choice emulator is a hardware debugging tool for developing user program via the 8 bit core g8mc family from hyundai microelectrincs co., ltd. [fig 5.1.1] environment for developing user program 5.1.1 configuration of emulator emulator choice is constructed by ? add-on board ? architecture. main board, control board are the base boards of choice and eva. board is GMS84512 eva board for tv application. l eva. chip ( GMS84512eva : 156 pin pga ) eva chip is special chip for the target micom. eva chip supports target micom ? s all function & includes interface logic with the emulator hardware. host computer emulator user system user system interface cable rs-232c tv choice target mcu debugger program
gms 84512 / 84524 5 - 2 5.1.2 cautionary notes 1. when changing board at expansion slot. you must ensure that power is off. 2. check and ensure that power for emulator & user system is supplied separately and if this is so, eva power option jumper must be open before using. 3. check polarity & connection location when connecting power cable, serial cable or interface cable to board. fig 5.1.2 connecting emulator & user system ? if emulator & user system use different power source ? if emulator & user system use same power source emulator eva board vuser main board gnd vcc user interface cable user system gnd vcc power source short source 2 emulator eva board vuser main board gnd vcc user system gnd vcc power source 1 power user interface cable open
gms 84512 / 84524 5 - 3 5.1.3 user interface socket pin assignment 1 hd 52 r50/ r 2 vd 51 r51/ g 3 r45/ pwm0 50 r52/ b 4 r44/ pwm1 49 r53/ y 5 r43/ pwm2 48 r00 6 r42/ pwm3 47 r01 7 r41/ pwm4 46 r02 8 r40/ pwm5 45 r03 9 r37/ pwm6 44 r04 10 r36/ pwm7 43 r05 11 r35/ sin/ cin3 42 r06 12 r34/ sclk 41 r07 13 r33/ sout 40 r10 14 r32/ pwm8 39 r11 15 r31/ int2 38 r12 16 r30/ int1 37 r13 17 r27/ ec3 36 r14 18 r26/ ec2 35 r15/ cin1 19 r25/ t2048 34 r16/ cin2 20 r24 33 r17/ cin0/ int3 21 r23 32 r20 22 r22 31 r21 23 test 30 reset 24 xin 29 osc1 25 xout 28 osc2 26 vss 27 vdd GMS84512/84524 e e e a. e sign indicates unconnected pin. fig 5.1.3. pin assign of GMS84512 / 84524 interface socket ? ? ?
gms 84512 / 84524 5 - 4 5.2 debugger { ref. gms800 series mds manual } the g8mc debugger is a s/w tool for developing user programs for the h y undai 8 bit core (g8mc family) . we prepared two types of debugger s/w. one is for the ms-dos and the other is for the ms-windows ( include ms-win95 ).
gms 84512 / 84524 5 - 5 5.3 assembler { ref. gms800 series mds manual } assembler is a s/w which translates source code to object code. especially gms800 series is like with high level language. 5.3.1 structure of source program list structure of source program list is shown below. 5.3.2 pseudo-instruction function pseudo-instruction constant definition equ (equal) rom data definition db (define byte ) dw (define word ) defining ram symbol ds (define storage ) address alteration org (origin ) program end end inserting external files include refer to external symbols public extrn (external ) outputting list files list nolist (no list ) title page macro definition macro endm (end of macro ) assembler oject program ( *.obj, *.ob2 ) source program list file ( *.lst ) comment field character string g8mc instruction, pseudo-instruction numeric constant, character constant,operator label: symbol operand field label field opcode field ; space : space
gms 84512 / 84524 5 - 6 5.3.3 structured commands l assignment statement ( = ) l if statement l for statement l while statement l switch statement l break statement 5.3.4 usage of assembler if else endif if endif for next do while switch case break case break : : default break ends relational operator ? ( less ) ? ( greater ) ? ? ( less or equal ) ? ? ( greater or equal ) ? ? ( equal ) ? ? ( not equal )
gms 84512 / 84524 5 - 7 . [syntex] [example] test.lst : list file test.obj : object file for hex file test.ob2 : object file for otp file [output files] /? displays help messages /l- list file is not displayed /c- error messages are not dipalyed command extension name (default : .asm) extension name (default : .asm) xasm8 < filename > [/option] xasm8 test.asm
gms 84512 / 84524 5 - 8 5.4 linker { ref. gms800 series mds manual } linker is a s/w that creates executable machine code from one or more object programs. g8mc linker generates motorola s-format. 5.4.1 usage of linker linker .hex file object program 1 .map file .sym file object program 2 object program n font file ( *.hl ) [syntex] /? displays help messages /m- .map file is not created /s- .sym file is not created /cpu= declaration target- mcu rom size /f specify font file name command extension name (default : . obj) extension name (default : . obj) xlink8 < filename 1> ... [/option] [example] xlink8 filename1 filename2 /f font.hl /cpu=84512 .otp file ..
gms 84512 / 84524 5 - 9 5.5 font editor { ref. gms800 series mds manual } g8mc font editor is osd font editor for GMS84512. ms-w indows version is supported. executable file name : fed8.exe l output files ? a .dat : data file for font editor a .hl : hexa file for otp ( it is converted to otp file by link ) a .hi : font hexa file for emulator upper bits a .lo : font hexa file for emulator lower bits ? ? notice : otp file must be converted from *.hl file by xlink8 using by /f option. 3 ? 2 1 0 00 08 18 index 13 10 7 6 5 4 20 28 38 30 40 48 58 50 60 68 78 70 x:03 y: 03 ( d ecimal ) left right up down reverse clear copy from undo character set ( 128 characters ) one character map ( 1 4 ? ? 18 ) edit menu
gms 84512 / 84524 5 - 10 5.6 otp socket adapter ( GMS84512/24 otp-ad ) GMS84512t/84524t is equivalent with GMS84512/84524, and it include programmable rom. prom writer socket adapter fig.5.6.1 top view of socker adapter switch ttl 52 sdip socket GMS84512/24 otp-ad prom font
gms 84512 / 84524 5 - 11 5 .6.1 otp chip writing method 1. programming voltage ( vpp ) is 12.5 v 2. if you write font rom, then set the switch to font. 3. and if you write program rom, then set the switch to prom. 4. you must use otp file not hex file. 5. you must set eprom type to 27c256 in prom writer. 6. you must program otp chip two times. because font rom and program rom are internally separated. l cautionary notes. for chip reliability, after write & aging, reading test is recommended. 0000 h ( 8 k bytes ) 1fef h 2000 h ( 8 k bytes ) 3fef h 2000 h ( gms84524 ) 5000 h ( GMS84512 ) 7fff h a000 h ( gms84524 ) d000 h ( GMS84512 ) ffff h ? ? buffer data will be write into GMS84512t at different address area by socket adapter. prom writer GMS84512t/84524t buffer ( ram ) otp file font 0000 h ( 8 k bytes ) 1fef h user program 2000 h ( gms84524 ) 5000 h ( GMS84512 ) 7fff h set switch to font set switch to prom
GMS84512/84524 user ? s manual table of contents 1. overview 2. cpu 3. peripheral function 4. control function 5. support tool 6. appendix
gms 84512 / 84524 a - 1 1.absoulte maximum ratings ( ta = 2 5 ? ) no. parameter symbol unit ratings etc. 1 supply voltage v dd ? -0.3 ? - 6.0 2 input nmos open drain v in1 ? -0. 3 ? - 9.0 voltage etc. v in2 -0. 3 ? - vdd+0.3 3 output 1 port peak i peak max. | 1 0 | current total i avg max. | 5 0 | 4 operating temeperature t opr ? -1 0 ? - 70 5 starage temperature t stg ? -40 ? - 125 2. dc characteristics ( ) ( vss = 0 ? , ta = -1 0 ? - 7 0 ? , f (xin) = 4 mhz ) no. parameter symbo l unit test conditions min. typ. max. etc. 1 supply voltage vdd ? 4.5 5 5.5 2 supply voltage idd ma f(x in ) =4 mhz, reset state 10 20 3 supply current in stop mode istop ? input = vss 10 300 *1 *1 : when port output current do not sink or source. specification
gms 84512 / 84524 a - 2 3. dc characteristics ( ) ( vdd = 5 v ? ? 10%,vss = 0 ? , ta = -1 0 ? - 7 0 ? ,f (xin) = 4 ? ) no. parameter pin symbo l unit test specification etc. condition min. typ. max. 1 ' h ? input reset, test, xin, schmitt *1 input v ih ? 0.8 v dd v dd voltage other port *2 0.7 v dd v dd 2 ? l ? input reset, test, xin, schmitt *1 input ? 0 0.12 v dd voltage other port *2 0 0.3 v dd 3 ' h ? input current all input pins i ih ? v i = v dd -5.0 5.0 4 ? l ? input current all input pins i il ? v i = v ss -5.0 5.0 5 hysteresis schmitt *1 input v t+ ? 0.3 1.0 reset v t- 0.2 0.7 6 ' h ? output voltage r0, r1 0 ? - r16, r2, r3 3 ? - r35, r5 v oh ? i oh = -5 vdd -1 fig. a.1 ref. 7 ? l ? output voltage r0, r1 0 ? - r16, r2, r3 2 ? - r37, r4, r5 v ol ? i ol = 5 1.0 fig. a.1 ref. 8 ram data retension v dd v ram ? at clock stop 2.0 *1 . schmitt input : ec3, ec2, sin, sclk, int 1 ? - int3, hd, vd *2. other ports : r0, r1, r2, r3 1.0v 0.8 0.6 0.4 0.2 0 0 6 4 2 0 1 0 8 - 6 - 4 - 2 - 1 0 - 8 1.0v 0.8 0.6 0.4 0.2 0 v ol v dd - v oh spec. fig. a.1 port output characteristics ( @ v dd = 5 v ) i ol i oh spec. hot ( 7 5 ? ) room cold ( -1 0 ? )
gms 84512 / 84524 a - 3 4. a/d comparator characteristics ( vdd = 5 v ? ? 10%,vss = 0 ? , ta = -1 0 ? - 7 0 ? ,f (xin) = 4 ? ) no. parameter pin symbol unit specification etc. min. typ. max. 1 analog input voltage rage cin 0 ? - cin3 v ain v v ss v dd 2 accuracy lsb ? ? 1 5. ac characteristics 5.1 input conditions ( main clock, reset, int, ec, osd clock, vd, hd ) ( vdd = 5 v ? ? 10%,vss = 0 ? , ta = -1 0 ? - 7 0 ? ,f (xin) = 4 ? ) no. parameter pin symbol unit specification etc. min. typ. max. 1 main clock frequency xin f cp mhz 3 4 5 2 system clock cycle t sys ns 400 500 667 3 oscillation stable time xin, xout t st ms 20 4 external clock pulse width xin t cpw ns 80 5 external clock transition timer xin t rcp, t fcp ns 20 6 interrupt pulse width int1~int3 t iw t sys 2 8 ? l ? reset input pulse width reset t rst t sys 8 9 event counter pulse width ec2, ec3 t ecw t sys 2 10 event counter transition timer ec2, ec3 t rec, t fec ns 20 11 osd clock frequency osc1, osc2 f osd mhz 4 6 8 l-c oscillator 12 v-sync pulse width vd t vdw 2 13 h-sync pulse width hd t hdw 2 ? ? fig. a-2 ref.
gms 84512 / 84524 a - 4 5.2 serial transfer ( vdd = 5 v ? ? 10%,vss = 0 ? , ta = -1 0 ? - 7 0 ? ,f (xin) = 4 ? ) no. parameter pin symbol unit test condition specification etc. min. typ. max. 1 serial input clock cycle sclk t scyc 2 t sys+ 200 2 serial input clock pulse width sclk t sck t sys +70 3 serial input clock transition time sclk t rsck, t fsck 30 4 serial input data transition time sin t rsin, t fsin 30 5 serial input data sin t sus external sclk 100 set-up time internal sclk 200 6 serial input data hold time sin t hs external sclk t sys +100 7 serial output clock cycle sclk t scyc load = 50 4 t sys 16 t sys 8 serial output clock pulse width sclk t sck 2t sys - 30 9 serial output transition time sclk t rsck, t fsck 30 10 serial output data delay time sout t ds 100 ? ? fig. a-3 ref.
gms 84512 / 84524 a - 5 reset xin t cpw t cpw 0.5 v vdd-0.5v t cpw 1/f cp t cpw int1 int2 int3 0.2 vdd 0.8 vdd t iw t iw t rst 0.2 vdd vd hd ec2 ec3 0.2 vdd 0.8 vdd 0.8 vdd t ecw t ecw t rec t fec t vdw, t hdw 0.2 vdd sin sclk 0.2 vdd sout 0.2 vdd 0.8 vdd t hs t sus t fsin t rsin 0.2 vdd 0.8 vdd t ds t rsck t fsck 0.8 vdd t scyc t sckw t sckw fig. a.2 clock, int, reset, ec, vd, hd input timing fig. a.3 serial i/o timing
gms 84512 / 84524 a - 6 GMS84512 package outline ( 52-pin sdip ) fig. a.4 52-pin s-dip package dimension [ unit : millimeters ] 0.25 0.05 15.24 0.25 0 ? - 15 13.97 0.25 26 h me GMS84512 / 84524 1 27 52 0.50 min. 3.24 0.20 1.778 0.25 1.02 0.25 0.47 0.13 4.83 max. 3.81 0.13 45.97 0.13 0.76 0.13 52ld s-sip 600mil
GMS84512t/24t programming manual
1 . device overview the GMS84512t/gms84524t are high-performance cmos 8-bit microcontroller with 12k/24k bytes of eprom. the device is one of gms800 family. the hyundai GMS84512t/gms8424t are powerful microcontroller which provides a highly flexible and cost effective solution to many embe dded control applica - tions. the GMS84512t/gms84524t provides the following standard features: 12k/24k bytes of eprom , 256 bytes of ram, 42 i/o lines, 16-bit or 8-bit timer/counter, on screen display, 5-bit a/d comparoto r, pwm, on-chip oscillator and clock circuitry. 2 . pin configuration GMS84512t gms84524t device name rom size GMS84512t 12k prom gms84524t 24k prom GMS84512t/gms84524t eprom programming 2
notes: (1) these pins must be connected to v ss , because these pins are input ports during programming, program verify and reading (2) these pins must be connected to v dd . (3) x out pin must be opened during programming. pin no. mcu mode otp mode 1 hd i (1) i 2 vd i (1) i 3 r45/pwm0 o (1) o 4 r44/pwm1 o (1) o 5 r43/pwm2 o (1) o 6 r42/pwm3 o (1) o 7 r41/pwm4 o (1) o 8 r40/pwm5 o (1) o 9 r37/pwm6 i/o (1) i 10 r36/pwm7 i/o (1) i 11 r35/sin/cin3 i/o a15 i 12 r34/sclk i/o a14 i 13 r33/sout i/o (1) i 14 r32/pwm8 i/o (1) i 15 r31/int2 i (2) i 16 r30/int1 i (2) i 17 r27/ec3 i/o ce i 18 r26/ec2 i/o oe i 19 r25/t2048 i/o a13 i 20 r24 i/o a12 i 21 r23 i/o a11 i 22 r22 i/o a10 i 23 test i v pp - 24 x in i (1) i 25 x out o (3) o 26 v ss i v ss - pin no. mcu mode otp mode 27 v dd i v dd - 28 osc2 o (3) o 29 osc1 i (1) i 30 reset i (1) i 31 r21 i/o a9 i 32 r20 i/o a8 i 33 r17/cin0/int3 i a7 i 34 r16/cin2 i/o a6 i 35 r15/cin1 i/o a5 i 36 r14 i/o a4 i 37 r13 i/o a3 i 38 r12 i/o a2 i 39 r11 i/o a1 i 40 r10 i/o a0 i 41 r07 i/o o7 i/o 42 r06 i/o o6 i/o 43 r05 i/o o5 i/o 44 r04 i/o o4 i/o 45 r03 i/o o3 i/o 46 r02 i/o o2 i/o 47 r01 i/o o1 i/o 48 r00 i/o o0 i/o 49 r53/y o (1) o 50 r52/b o (2) o 51 r51/g o (2) o 52 r50/r o (2) o i/o: input/output pin i: input pin o: output pin 52sdip package for GMS84512t/gms84524t GMS84512t/gms84524t eprom programming 3
3 . pin function (otp mode) v pp (program voltage) v pp is the input for the program voltage for programming the eprom. ce ( chip enable) ce is the input for programming and verifying internal eprom. oe (output enable) oe is the input of data output control signal for verify. a 0 ~a 15 (address bus) a 0 ~a 15 are address input pins for internal eprom. o 0 ~o 7 (eprom data bus) these are data bus for internal eprom. GMS84512t/gms84524t eprom programming 4
4 . programming the GMS84512t/gms84524t has two address ranges, font area and pgm area. therefore, the programme r should be program twice, each font and pgm. 4. 1 GMS84512t programming the font address ranges are from 0000 h to 1ff1 h and pgm addres ranges are from 5000 h to 7fff h in otp file. firstly, the programmer program the font data into the GMS84512t otp device ( from 2000 h to 3ff1 h ), and then program the pgm data into the GMS84512t otp device ( from d000 h to ffff h ). when the programmer write the font data 0000 h to 1ff1 h , consequently, the data actually will be written into address 2000 h to 3ff1 h of the GMS84512t otp device. and pgm data 5000 h to 7fff h , consequently, the data actually will be written into address d000 h to ffff h of the GMS84512t otp device. 1. the data format to be programmed is made up of motorola s1 format. ex) "motorola s1" format; s00800006d633634615c s1130800fffffcf0e3e7e7e7e7e7e7e7e7e3f0fc10 s1051800ffffe4 s1130000ffff9f87e3f3f3f3f3f3f3f3f3e3879f44 : s1051ff0ffbf2d s11307f0feffffffffffffffffffffffffffffff06 s10517f0fffef6 s12250009fe1c0711b003f1b003e1b043d1bf83c1b213b1bd13a1b00391b63381bc037c5 s123501f1bf0361b011b1bfb1a1b40053bff1a061a2f1a2e1b232d1b922c1b8f2b1b002a1c : s1217fe02001200120012001200120012001e6012001da021803bb0320010a1420017b s1057ffeff2f4f s9030000fc 2. down load above data into programmer from pc. 3. programming the data from address 0000 h to 1ff1 h and 5000 h to 7fff h into otp mcu, the data must be turned over respectively, and then record the data. ex) 00 ? ff, 76 ? 89, ff ? 00 etc. 4. of course, the check sum is result of the sum of whole data from address 0000 h to 7fff h in the file (not reverse data of otp mcu). caution : in the otp file, data ff h , bf h are written in 1ff0 h and 1ff1 h respectively. however, the otp chip was written already 49 h , 63 h in that addresses. therefore, that addresses should be skipped in programming or blank check. and should be treated ff h , bf h in checksum calculation ( read or verify). on the checksum calculation, not used area data should be regarded as ff h in otp file . when GMS84512t shipped, the blank data of GMS84512t is initially 00 h (not ff h ). font 0000 h ~ 1ff1 h pgm 5000 h ~ 7fff h GMS84512t/gms84524t eprom programming 5
(1) (1) (1) (1) address GMS84512t 7fff h addres s xxxxxxxx.otp universal programmer down loading program verify reading 5000 h file type: motorola s-format 2000 h 0000 h 1ff1 h d000 h ffff h 3ff1 h font font not used not used not used pgm pgm programming flow address GMS84512t device file xxxxxxxx.otp ff ff 9f : : ff bf : : ff ff : 9f e1 : ff 2f down loading program 0000 h 0001 h 0002 h : : 1ff0 h 1ff1 h : : 4000 h 4001 h : 5000 h 5001 h : 7ffe h 7fff h ff ff 9f : : ff bf : : ff ff : 9f e1 : ff 2f 00 00 60 : : 49 63 : : 00 00 : 60 1e : 00 d0 2000 h 2001 h 2002 h : : 3ff0 h 3ff1 h : : 4000 h 4001 h : a000 h a001 h : fffe h ffff h reading verify up loading data addres s data address programmer buffer checksum = ff+ff+9f+ + ff + bf + +ff+ff+ +9f+e1+ +ff+2f data 0000 h 0001 h 0002 h : : 1ff0 h 1ff1 h : : 4000 h 4001 h : 5000 h 5001 h : 7ffe h 7fff h programming example GMS84512t/gms84524t eprom programming 6
4. 2 gms84524t programming the font address ranges are from 0000 h to 1ff1 h and pgm addres ranges are from 2000 h to 7fff h in otp file. firstly, the programmer program the font data into the gms84524t otp device ( from 2000 h to 3ff1 h ), and then program the pgm data into the gms84524t otp device ( from a000 h to ffff h ). when the programmer write the font data 0000 h to 1ff1 h , consequently, the data actually will be written into address 2000 h to 3ff1 h of the gms84524t otp device. and pgm data 2000 h to 7fff h , consequently, the data actually will be written into address a000 h to ffff h of the gms84524t otp device. 1. the data format to be programmed is made up of motorola s1 format. ex) "motorola s1" format; s00700006d61696e53 s1130800fffffcf0e3e7e7e7e7e7e7e7e7e3f0fc10 s1051800ffffe4 s1130000ffff9f87e3f3f3f3f3f3f3f3f3e3879f44 : : s1130ff0bfffffffffffffffffffffffffffffff3d s1051ff0ffbf2d s12220009fe1c0711b003f1b003e1b183d1b803c1b283b1bd33a1b00391b63381bff3711 s123201f1bf0361bfc1b1bfb1a1b40051b0f061bff433a415b00ba4a8fe9bbe72fed3a4083 : : s1217fe0670b670b670bff5f670b670b670bce0c670bfa0bb30ba00d670b991f670b1d s1057ffeff5f1f s9030000fc 2. down load above data into programmer from pc. 3. programming the data from address 0000 h to 1ff1 h and 2000 h to 7fff h into otp mcu, the data must be turned over respectively, and then record the data. ex) 00 ? ff, 76 ? 89, ff ? 00 etc. 4. of course, the check sum is result of the sum of whole data from address 0000 h to 7fff h in the file (not reverse data of otp mcu). caution : in the otp file, data ff h , bf h are written in 1ff0 h and 1ff1 h respectively. however, the otp chip was written already 49 h , 63 h in that addresses. therefore, that addresses should be skipped in programming or blank check. and should be treated ff h , bf h in checksum calculation ( read or verify). on the checksum calculation, not used area data should be regarded as ff h in otp file . when gms84524t shipped, the blank data of gms84524t is initially 00 h (not ff h ). font 0000 h ~ 1ff1 h pgm 2000 h ~ 7fff h GMS84512t/gms84524t eprom programming 7
(1) (1) (1) (1) address gms84524t 7fff h addres s xxxxxxxx.otp universal programmer down loading program verify reading 2000 h file type: motorola s-format 2000 h 0000 h 1ff1 h a000 h ffff h 3ff1 h font font not used not used pgm pgm programming flow address gms84524t device file xxxxxxxx.otp ff ff 9f : : ff bf 9f e1 c0 71 : : ff 5f down loading program 0000 h 0001 h 0002 h : : 1ff0 h 1ff1 h 2000 h 2001 h 2002 h 2003 h : : 7ffe h 7fff h ff ff 9f : : ff bf 9f e1 c0 71 : : ff 5f 0000 h 0001 h 0002 h : : 1ff0 h 1ff1 h 2000 h 2001 h 2002 h 2003 h : : 7ffe h 7fff h 00 00 60 : : 49 63 : 60 1e 3f 8e : : 00 a0 2000 h 2001 h 2002 h : : 3ff0 h 3ff1 h : a000 h a001 h a002 h a003 h : : fffe h ffff h reading verify up loading data addres s data addres s data programmer buffer checksum = ff+ff+9f+ + ff + bf +9f+e1+c0+71+ +ff+5f programming example GMS84512t/gms84524t eprom programming 8
5 . device operation mode (t a = 25 c 5 c) mode ce oe a 0 ~a 15 v pp v dd o 0 ~o 7 read x x v dd 5.0v d out output disable v ih v ih x v dd 5.0v hi-z programming v il v ih x v pp v dd d in program verify x x v pp v dd d out notes: 1. x = either v il or v ih 2. see dc characteristics table for v dd and v pp voltages during programming. 6 . dc characteristics (v ss =0 v, t a = 25 c 5 c) symbol item min typ max unit test condition v pp intelligent programming 12.0 - 13.0 v v dd (1) intelligent programming 5.75 - 6.25 v i pp (2) v pp supply current 50 ma ce =v il i dd (2) v dd supply current 30 ma v ih input high voltage 0.8 v dd v v il input low voltage 0.2 v dd v v oh output high voltage v dd -1.0 v i oh = -2.5 ma v ol output low voltage 0.4 v i ol = 2.1 ma i il input leakage current 5 ua notes: 1. v dd must be applied simultaneously or before v pp and removed simultaneously or after v pp . 2. the maximum current value is with outputs o 0 to o 7 unloaded. GMS84512t/gms84524t eprom programming 9
notes: 1. the input timing reference level is 1.0 v for a v il and 4.0v for a v ih at v dd =5.0v 2. to read the output data, transition requires on the oe from the high to the low after address setup time t as . waveform inputs outputs must be steady may change from h to l may change from l to h do not care any change permitted does not apply w ill be steady w ill be changing from h to l w ill be changing from l to h changing state unknown center line is high impedance "off" state switching waveforms address valid t oe valid output t dh addresses oe output high-z v ih v il v ih v il v ih v il t as (2) reading waveforms GMS84512t/gms84524t eprom programming 10
notes: 1. the input timing reference level is 1.0 v for a v il and 4.0v for a v ih at v dd =5.0v t dfp addresses data high-z v ih v il 12.5v v dd v pp v dd ce oe 6.0v 5.0v t as t ds t vps t vds t opw t pw t oes t oe program program verify t dh v ih v il v ih v il v ih v il t ah address stable data in stable data out valid programming algorithm waveforms GMS84512t/gms84524t eprom programming 11
7 . ac reading characteristics (v ss =0 v, t a = 25 c 5 c) symbol item min typ max unit test condition t as address setup time 2 us t oe data output delay time 200 ns t dh data hold time 0 ns notes: 1. v dd must be applied simultaneously or before v pp and removed simultaneously or after v pp . 8 . ac programming characteristics (v ss =0 v, t a = 25 c 5 c; see dc characteristics table for v dd and v pp voltages.) symbol item min typ max unit condition* (note 1) t as address set-up time 2 us t oes oe set-up time 2 us t ds data setup time 2 us t ah address hold time 0 us t dh data hold time 1 us t dfp output disable delay time 0 us t vps v pp setup time 2 us t vds v dd setup time 2 us t pw program pulse width 0.95 1.0 1.05 ms intelligent t opw ce pulse width when over programming 2.85 78.75 ms (note 2) t oe data output delay time 200 ns *ac conditions of test input rise and fall times (10% to 90%) . . . 20 ns input pulse levels . . . . . . . . . . . . . . 0.45v to 4.55v input timing reference level . . . . . . . . 1.0v to 4.0v output timing reference level . . . . . . . 1.0v to 4.0v notes: 1. v dd must be applied simultaneously or before v pp and removed simultaneously or after v pp . 2. the length of the overprogram pulse may vary from 2.85 msec to 78.75 msec as a function of the iteration counter value x (intelligent programming algorithm only). refer to page 13. GMS84512t/gms84524t eprom programming 12
start v dd = 6.0v v pp = 12.5v x = 0 program one 1 ms pulse increment x verify byte verify one byte last address ? v dd = v pp = 5.0v compare all bytes to original data device passed increment address yes no fail pass fail pass no yes fail pass device failed program one pulse of 3x msec duration x = 25 ? address= first location intelligent programming algorithm GMS84512t/gms84524t eprom programming 13

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